A54SX16P PQFP Search Results

actel cqfp 84

Abstract: A1010B ACTEL FBGA 144
Contextual Info: v3.0 Package Options: User I/Os per Package C om m e r c i a l / I nd us t r i a l D ev i c e s A54SX16 A54SX16P A54SX32 130 175 175 174 81 81 81 A54SX08 A54SX72A SX A54SX32A A54SX16A 44 A54SX08A PLCC SX-A eX256 Pins eX128 Package eX64 eX 68 84 PQFP 69 100

Contextual Info: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates

54sx08

Abstract: THERMAL Fuse m20 tf 115 c
Contextual Info: v 3 .0 54SX Family FPGAs Leading Edge Performance • 100%Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3VOperation with 5.0VInput Tolerance • 3.7 nsClock-to-Out Pi n-to-Pi n • Very Low Power Consumption • 0.1 ns Input Set-Up

a54sx72a

Abstract: TQFP-176 footprint A54SX16A A54SX32A-
Contextual Info: Application Note SX to SX-A Design Migration I n tro du ct i on • Configurable Output State During Power Up: All outputs can be programmed to either weak resistor pull up or weak resistor pull down for output tristate. SX-A is fabricated using a 0.22/0.25µ CMOS process. These

A54SX16A

Abstract: A54SX72A A54SX08A A54SX32 A54SX32A AC157 PQ208 A54SX08 A54SX16 A54SX16P PQFP
Contextual Info: Application Note AC157 SX to SX-A Design Migration I n tro du ct i on • Configurable Output State During Power Up: All outputs can be programmed to either weak resistor pull up or weak resistor pull down for output tristate. SX-A is fabricated using a 0.22/0.25µ CMOS process. These

THERMAL Fuse m20 tf 115 c

Abstract: SX v3.1 REQ64 A54SX08 A54SX16 A54SX32 PAR64 313 pin PBGA fq1200 THERMAL Fuse l20 tf 115 c
Contextual Info: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates

THERMAL Fuse m20 tf 115 c

Abstract: 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 circuit diagram of motherboard W2-081 ac 171
Contextual Info: v3.1 54SX Family FPGAs Le a di ng E dg e P er f or m a nc e F ea t u r es • 320 MHz Internal Performance • 66 MHz PCI • 3.7 ns Clock-to-Out Pin-to-Pin • CPLD and FPGA Integration • 0.1 ns Input Set-Up • Single Chip Solution • 0.25 ns Clock Skew

Contextual Info: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew

54SX

Abstract: A54SX08 A54SX16 A54SX32 PAR64 REQ64 38VCC 54SX16P
Contextual Info: v3.0.1 54SX Family FPGAs Lead ing E dge P er f or m ance Feat ur es • 320 MHz Internal Performance • 66 MHz PCI • 3.7 ns Clock-to-Out Pin-to-Pin • CPLD and FPGA Integration • 0.1 ns Input Set-Up • Single Chip Solution • 0.25 ns Clock Skew • 100% Resource Utilization with 100% Pin Locking

ACTEL BGA329

Abstract: LRD12 54SX A54SX08 A54SX16 A54SX32 PAR64 REQ64 LRD-12 A54SX16P PQFP
Contextual Info: -m e te f v 3 .0 - m 54SX Fami ly FPGAs Leadi ng Edge P e r f o r m a n c e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-toOut Pin-to-Pin • \fcry Low Power Consumption

sx 2082

Contextual Info: v3.0 54SX Family FPGAs Lead ing E dge P er f or m ance Feat ur es • 320 MHz Internal Performance • 66 MHz PCI • 3.7 ns Clock-to-Out Pin-to-Pin • CPLD and FPGA Integration • 0.1 ns Input Set-Up • Single Chip Solution • 0.25 ns Clock Skew • 100% Resource Utilization with 100% Pin Locking

k16 a21

Abstract: 313-pin
Contextual Info: ^ c M J P relim inary • v 1 .1 54SX Family FPGAs Features • 3.3VOperation with 5.0VInput Tolerance Hi gh P e r f o r m ance • Low Power Consumption • 320 MHz Internal Performance • Deterministic, User-ControlIableTiming • 4.0 nsClock-to-Out Pi n-to-Pi n

THERMAL Fuse m20 tf 115 c

Abstract: 54SX16A actel fpga 54sx32 54SX32
Contextual Info: ^ c te l v 2 .0 54SX Family FPGAs L ea d in g Edge Pe rform an ce • 100% Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3V Operation with 5.0V Input Tolerance • 3.7 ns Clock-to-Out Pm-to-Pin • Very Low Power Consumption

A40MX04

Abstract: ACTEL FBGA 144 A42MX09 A42MX24 A42MX16
Contextual Info: Actel FPGA Selector Guide Commercial & Industrial Devices eX SX-A SX MX ProASIC System Typical Gates Gates Logic Dedicated Max Modules Flip-Flops Flip-Flops SRAM Max I/O 2.5V CMOS 3.3V CMOS 5V CMOS 5V Tolerant 3.3V 5V Slew Rate Routed Hardwired Bits Available

A500K180

Abstract: A42MX16 ACTEL FBGA 144 A42MX09
Contextual Info: Actel FPGA Selector Guide Commercial & Industrial Devices SX-A SX MX ProASIC System Typical Gates Gates Logic Dedicated Max SRAM Max I/O 2.5V CMOS 3.3V CMOS 5V CMOS 5V Tolerant 3.3V 5V Slew Rate Routed Hardwired 33 MHz 66 MHz Temp Speed Bits Available drive

PMX32

Abstract: pqfp 3.2mm footprint a54sx72a
Contextual Info: Actel FPGA Selector Guide System Gates Typical Gates Logic Modules Dedicated FlipFlops Max FlipsFlops SRAM Bits Max I/O Available 2.5V CMOS Drive 3.3V CMOS Drive 5V CMOS Drive 5V Tolerant Inputs 3.3V PCI I/O 5V PCI I/O Slew Rate Control Routed Clocks HardWired

LRD12

Abstract: IRD12
Contextual Info: 54SX Family FPGAs Features • 3.3VOperation with 5.0VInput Tolerance High • Low Power Consumption Perform ance • 320 MHz I nternal Performance • Deterministic, User-ControlIableTiming • 4.0 ns Cl ock-to-Out Pin-to-Pin • Unique, In-System Diagnostic and Debug Facility with

actel cqfp 84

Abstract: actel a1020b RT1425A actel a1010b actel 172 cqfp
Contextual Info: Package Options: User I/Os per Package January 1999 1999 Actel Corporation 1 Commercial/Industrial Devices RQFP VQFP TQFP BGA CPGA CQFP 129 172 172 125 176 34 57 69 69 72 83 72 72 57 125 125 152 125 176 176 202 176 176 202 57 78 112 129 78 144 78 112 144

FBGA-484

Abstract: FBGA484 ACTEL FBGA 144
Contextual Info: Actel FPGA Selector Guide Ava i l a b l e Co m m e rc i a l & In d u s t r i a l De v i c e s 54SX-A 54SX 40MX 42MX ProASIC System Typical Gates Gates Logic Max SRAM Max I/O 2.5V CMOS 3.3V CMOS 5V CMOS 5V Tolerant 3.3V 5V Slew Rate Flip Flops Bits Available

QFN108

Abstract: QFN-132 kl1-v1 208 pin rqfp drawing qfn132 RT3PE3000L CQ256 DIMENSIONS pqfp 100 actel package mechanical drawing Actel A40MX04 PBGA 23X23 0.8 pitch
Contextual Info: v 11. 2 Package Mechanical Drawings Ceramic Pin Grid Array 84-Pin CPGA Top View 0.050" ± 0.010" Pin #1 ID 0.045" 0.055" 0.015" 0.018" ± 0.002" 0.100" BSC 1.100" ± 0.020" square 0.072" 0.088" L 0.120" 0.140" Side View K J H G F 1.000" BSC E D C B A 1 2 3

CQFP 256 PIN actel

Contextual Info: Pr el i mi nar y v 1. 3 54SX Family FPGAs RadTolerant and HiRel Features • 100% Resource Utilization with 100% Pin Locking RadTolerant 54SX Family • Mixed Voltage Support—3.3V Operation with 5.0V Input Tolerance • Tested Total Ionizing Dose TID Survivability Level

Contextual Info: P r e l i m i n a r y v 1 .3 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput Tolerance • Tested Total IonizingDose TID Survivability Level

Contextual Info: 54SX Family FPGAs RadTolerant and HiRel Features R a d T ole ran t 54SX Family • • • • • TestedTotal Ionizing Dose TID Survivability Level Devices Avail able from Tested Lots Radiation Performance to 100K Rads Up to 160 MHz On-Chip Performance

Contextual Info: Preliminary v 1 .2 54SX Family FPGAs RadTolerant and HiRel Features • 100%Resource Utilization with 100%Pin Locking Rad T o lera nt 54SX Family • Mixed Voltage Support— 3.3V Operation with 5.0V Input • TestedTotal Ionizing Dose TID Survivability Level