A54SX Search Results

RT54SX72S

Abstract: A54SX72A RT54SX-S Signal Path Designer
Contextual Info: Techni c al Br i ef Using A54SX72A and RT54SX72S Quadrant Clocks Ar ch it e c tu r al Ov er vi ew The A54SX72A and RT54SX72S devices offer four quadrant clock networks QCLK0, 1, 2, and 3 that can be driven from external points or from internal logic signals within the

actel

Abstract: A54SX32 54SX A54SX16
Contextual Info: Errata v2.0 54SX Family FPGAs RadTolerant and HiRel Errata In Table 1 on page 8, the Maximum Input Tolerance for the A54SX16 and A54SX32 devices is incorrect. Here is how the table should appear. Table 1 • Supply Voltages Devices A54SX16 A54SX32 RT54SX16

vhdl code for manchester decoder

Abstract: manchester verilog decoder MIL-HDBK-1553A 1553b VHDL 1553b bu-63147 fpga 1553B SA30L Verilog implementation of a Manchester Encoder/Decoder
Contextual Info: v3.0 MIL-STD-1553B Remote Terminal Core1553BRT Pr od uc t S um m ary De vel opm en t Sy s te m In t e n d e d U s e • Complete 1553BRT Implementation, Implemented in an A54SX32A • 1553B Remote Terminal RT • DMA Backend Interface to External Memory

actel cqfp 84

Abstract: A1010B ACTEL FBGA 144
Contextual Info: v3.0 Package Options: User I/Os per Package C om m e r c i a l / I nd us t r i a l D ev i c e s A54SX16 A54SX16P A54SX32 130 175 175 174 81 81 81 A54SX08 A54SX72A SX A54SX32A A54SX16A 44 A54SX08A PLCC SX-A eX256 Pins eX128 Package eX64 eX 68 84 PQFP 69 100

multiplexor

Abstract: RT54SX72S RT54SX-S A54SX72A AC169 Signal Path Designer
Contextual Info: Application Note AC169 Using A54SX72A and RT54SX72S Quadrant Clocks Ar ch it e c tu r al Ov er vi ew The A54SX72A and RT54SX72S devices offer four quadrant clock networks QCLK0, 1, 2, and 3 that can be driven from external points or from internal logic signals within the

528-58

Abstract: A54SX16 A54SX16-2 AC135 VQ100 K28-1 pd6bc
Contextual Info: Application Note AC135 Implementing an 8b/10b Encoder/Decoder for Gigabit Ethernet in the Actel SX FPGA Family Introduction This application note describes how an Actel A54SX16 FPGA was used to implement an 8b/10b encoder/decoder function for a Gigabit Ethernet router.

ACTEL

Abstract: A54SX32 errata
Contextual Info: Errata v2.0 54SX Family FPGAs Errata In Table 1 on page 8, the supply voltage is incorrect. Here is how the table should appear. A54SX16-P has three different entries because it is capable of both a 3.3V and a 5V drive. Table 1 • Supply Voltages VCCA VCCI

Actel A54sx08a

Abstract: A54SX08A
Contextual Info: Application note Using Actel’s A54SX08A FPGA to Interface a PowerQUICC Microprocessor to a MUSIC-IC LANCAM I n tro du ct i on Content Addressable Memory CAM is a special memory designed to accelerate any application that requires extremely fast searches of list-based data such as database

fluke 8050a

Abstract: A54SX08 A54SX08-2 EPM7256A
Contextual Info: A ppl i cati on N ot e Power Requirements: Actel A54SX08 vs. Altera CPLDs In t ro d u c t i o n FPGAs have traditionally been perceived as inferior in performance to CPLDs. Actel’s high-performance antifuse SX family, however, offers both superior speed and reduced

0D100

Abstract: pd6bc
Contextual Info: Appl i cat i o n N ot e Implementing an 8b/10b Encoder/Decoder for Gigabit Ethernet in the Actel SX FPGA Family Introduction This application note describes how an Actel A54SX16 FPGA was used to implement an 8b/10b encoder/decoder function for a Gigabit Ethernet router.

A54SX08A

Abstract: AC148 MPC855T MU9C4480L
Contextual Info: Application Note AC148 Using Actel’s A54SX08A FPGA to Interface a PowerQUICC Microprocessor to a MUSIC-IC LANCAM I n tro du ct i on Content Addressable Memory CAM is a special memory designed to accelerate any application that requires extremely fast searches of list-based data such as database

C4466

Abstract: FG484 CQ256 FG144 D1425 ACTEL SI-SXA-APATQ100-A-KIT SI-SX72-ACQ256SFG484 A54SX72A C4002
Contextual Info: 0HFKDQLFDO 'UDZLQJV IRU WKH $GDSWHU %RDUG S/N Package Device Actel Part Number 1 CQ256 to FG484 For A54SX72A and RT54SX72S devices SI-SX72-ACQ256SFG484 Ironwood Electronics Part Number: CQ256 to FG484 adapter for SX32 And SX72.pdf C4002

fluke 8050a

Abstract: fluke 8050a digital multimeter Fluke 8050A multimeter A54SX08 A54SX08-2 AC138 EPM7256A E3615A
Contextual Info: Application Note AC138 Power Requirements: Actel A54SX08 vs. Altera CPLDs In t ro d u c t i o n FPGAs have traditionally been perceived as inferior in performance to CPLDs. Actel’s high-performance antifuse SX family, however, offers both superior speed and reduced

54SX32

Abstract: A54SX32 A54SX32A A54SX72A PAR64 REQ64 54SX32A il 074
Contextual Info: Preliminary v1.0 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • QML Certified Devices • 215 MHz System Performance Military Temperature • 100% Military Temperature Tested (–55°C and +125°C) • 5.3ns Clock-to-Out (Pin-to-Pin) (Military Temperature)

TMS 3833

Abstract: actel package mechanical drawing DIL 8 293 133A PCP bulletin 451 qml-38535 A54SX16 A54SX16-1 7540 Group SKs smd 69
Contextual Info: REVISIONS DATE YR-MO-DA _APPROVED A Added devices 03 and 04, editorial changes to table I and the appropriate paragraphs throughout the document. Added figures for bond pad locations for device 03.

Contextual Info: v3.0 SX-A Family FPGAs Leading-Edge P erfo rm an c e • 250 MHz System Performance • 3.8ns Clock-to-Out Pad-to-Pad • 350 MHz Internal Performance S p ec ific atio n s • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins

54sx08

Abstract: THERMAL Fuse m20 tf 115 c
Contextual Info: v 3 .0 54SX Family FPGAs Leading Edge Performance • 100%Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3VOperation with 5.0VInput Tolerance • 3.7 nsClock-to-Out Pi n-to-Pi n • Very Low Power Consumption • 0.1 ns Input Set-Up

Contextual Info: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew

verilog code for fir filter using DA

Abstract: A3P1500 vhdl code of 32bit floating point adder digital FIR Filter verilog code digital FIR Filter VHDL code fir vhdl code FIR Filter verilog code vhdl code for floating point adder IQ GENERATOR CODE WITH VHDL RTAX2000
Contextual Info: CoreFIR Finite Impulse Response FIR Filter Generator Product Summary Core Deliverables • Intended Use • – Finite Impulse Response (FIR) Filter for Actel FPGAs • Key Features • – • Self-Checking – Executable Tests Generated Output against Algorithm

1553b VHDL

Abstract: Actel 1553b fpga 1553B transistor BC 584 MIL-STD-1553B FPGA RT MIL-STD-1553B ACTEL FPGA manchester verilog decoder vhdl code manchester encoder mil-std-1553b SPECIFICATION transistor BC 490
Contextual Info: Core1553BBC MIL-STD-1553B Bus Controller Product Summary • Intended Use • 1553B Bus Controller BC • DMA Backend Interface to External Memory Synthesis and Simulation Support Key Features • • • • • • Supports MIL-STD-1553B Interfaces to External RAM

HiRel a54sx72a unused

Contextual Info: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

verilog code for implementation of des

Abstract: vhdl code for DES algorithm RTAX1000S rtax1000 verilog code for des vhdl code for des decryption data encryption standard vhdl wireless encrypt
Contextual Info: Core3DES Product Summary Intended Use • Whenever Data Is Transmitted Across an Accessible Medium wires, wireless, etc. • E-Commerce Transactions, Where Dedicated Encryption/ Decryption Hardware Can Ease the Load on Servers Core Deliverables • Evaluation Version

LGA 478 SOCKET PIN LAYOUT

Abstract: RTAX2000
Contextual Info: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg

4 BIT ALU design with vhdl code using structural

Abstract: RTAX1000S CORE8051 vhdl code for accumulator vhdl code for data memory 80C31 APA150-STD ASM51 R22-BH 80C31 instruction set
Contextual Info: Core8051 Product Summary • Intended Use • • • Embedded System Control Communication System Control I/O Control • • • Key Features • • • • • • • • • Supported Families 100% ASM51 8051/80C31/80C51 Compatible Instruction Set 1