A14100BP Search Results

A1425A-3

Contextual Info: ACT3PCI.fm v6 Page 1 Tuesday, August 12, 1997 11:17 AM Accelerator Series FPGAs: ACT 3 PCI-Compliant Family F e atures • Up to 10,000 Gate Array Equivalent Gates. • Up to 250 MHz On-Chip Performance. • 9.0 ns Clock-to-Output. • Up to 1,153 Dedicated Flip-Flops.

Actel

Abstract: Actel a1225xl ACTEL A1240xl A1280RH 1280xl 1240XL actel 1240xl 32200DX
Contextual Info: High-Level Design Benchmark Report Engineers are faced with FPGA designs that continue to get larger and more complex while design cycles get shorter. To manage complex designs quickly, many engineers use HighLevel design languages VHDL or Verilog HDL to describe

ACTEL CROSS REFERENCE

Abstract: atmel 424 actel a10v20b fpga da altera Actel Accelerator fpga XC4005E/XC4005 EPM5130 06M7374 Atmel 224 atmel 55000
Contextual Info: CMOS ASIC Converting FPGAs and PLDs to Atmel Gate Arrays Introduction Atmel is one of the only companies that designs and manufactures field programmable gate arrays FPGAs , programmable logic devices (PLDs) and high performance gate arrays. Atmel offers a seamless, direct conversion

ACT 3 accelerator FPGAs

Contextual Info: ^ c te l Accelerator Series FPGAs: ACT 3 PCI-Compliant Family F e a tu re s • Up to 10,000 Gate Array Equivalent Gates. • Up to 250 MHz On-Chip Performance. Highly Predictable, Synthesis-Friendly Architecture Supports High-Level Design Methodologies. 100% Module Utilization with Automatic Place and Route

ACT 3 Accelerator

Abstract: ACT 3 accelerator FPGAs Actel Accelerator fpga datasheet DLM8 A1425A-3
Contextual Info: Accelerator Series FPGAs – ACT 3 PCI-Compliant Family Features • Up to 10,000 Gate Array Equivalent Gates. • Up to 250 MHz On-Chip Performance. • 9.0 ns Clock-to-Output. • Up to 1,153 Dedicated Flip-Flops. • Up to 228 User-Programmable I/O Pins.

RT54SX72SCQ208

Abstract: A42MX16 RT54SX32S-CQ208 CQ208 CQ256
Contextual Info: v3.0 Component Selector Guide PCI 5.0 Volt Tolerant — 5 Volt I/O — Yes Yes Yes — — Yes 3.3 Volt I/O 3,000 2.5 Volt I/O Gates 36 JTAG I/O User I/O C, I SRAM Bits Screening –F, Std, –P Wide Decodes Speed Grade CS49 Flip-Flops/Dedicated Max Package

Contextual Info: CorePCI Target+DMA Product Summary Version Intended Use This data sheet defines the functionality of Version 2.0 and later macros. • High-Performance Applications PCI Target and DMA Master – 32-Bit, 33 MHz, 5.0V ACT 3, 42MX – 32-Bit, 33 MHz, 3.3V (42MX)

A1280XL

Abstract: A32100DX A3265DX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 A1225XL
Contextual Info: Component Selector Guide Mixed Voltage FPGA Selector Guide These FPGAs operate in 5.0V-only, 3.3V-only, or mixed 5.0V/3.3V systems. Device Type Speed Option2 Temp.3 Range 44 Std, -1, -2, -3 68 Std, -1, -2, -3 100 Std, -1, -2, -3 Pkg1 No. Pins PL PL PQ User

40MX

Abstract: 42MX
Contextual Info: 3.1.1 Supplement for Update 1 This document describes the new features and enhancements of Designer Series 3.1.1 Update 1. This is the same information that is contained in the Designer Series Development System 3.1.1 Release Notes. It also contains information about the Designer Series 3.1.1

3265DX

Abstract: 40MX 42MX RH1020
Contextual Info: Designer Series Development System 3.1.1 Release Notes This document describes the new features and enhancements of the Designer Series Development System 3.1.1 and the Designer Series 3.1.1 Update 1. It also contains instructions on where to find Designer Series software supplement files containing

CQ256

Abstract: CQ208 4PMX 4pm smd
Contextual Info: te /e • / Speed Grade JTAG I/O 3.3 Volt 5 Volt PCI 5.0 Volt Tolerant at 3.3V VQ100 Std, - 1 , - 2 , - 3 129 8,000 256 512 - — Yes Yes — — Yes PQ208 Std, - 1 , - 2 , - 3 129 8,000 256 512 — — Yes Yes — — Yes TQ144 Std, - 1 , - 2 , - 3 129 8,000

Contextual Info: Component Selector Guide 5 Volt FPGA S e le c to r Guide Device Type A1225XL A1240XL A3265DX A1280XL A32100DX A32140DX A32200DX A32300DX A32400DX * Pkg1 No. Pins PG PL Speed Option2 Temp.3 Range 100 S td ,-1 ,-2 84 S td ,-1, -2 PQ 100 VQ PG User I/O Logic

MICRON POWER RESISTOR Mos

Contextual Info: 4 - A C T 3P C L fm v6 P a g e l Tuesday, August 12, 1997 11:17 AM Accelerator Series FPGAs: PCT 3 PQ-Gompliant Family £g"b£ t ta «1 fttlM IHs «5 • Up to 10,000 Gate Array Equi\alent Gates. FEghly Predictable, Synthesis-Friendly Architecture Supports FEgh-Level Design IVfethodologies.

Contextual Info: BACK Accelerator Series FPGAs – ACT 3 PCI-Compliant Family Features • Up to 10,000 Gate Array Equivalent Gates. • Up to 250 MHz On-Chip Performance. • 9.0 ns Clock-to-Output. • Up to 1,153 Dedicated Flip-Flops. • Up to 228 User-Programmable I/O Pins.

Pl84

Contextual Info: Component Selector Guide April 1999 1999 Actel Corporation 1 Package Speed Grade SRAM Bits JTAG I/O 3.3 Volt 5 Volt PCI 5.0 Volt Tolerant at 3.3V VQ100 Std, –1, –2, –3 78 8,000 256 512 — — Yes Yes — — Yes PQ208 Std, –1, –2, –3 129 8,000

Contextual Info: CorePCI Target Product Summary Version Intended Use This data sheet defines the functionality of Version 2.0 and later macros. • High-Performance PCI Target Applications – 32-Bit, 33 MHz, 5.0V ACT 3, 42MX General Description – 32-Bit, 33 MHz, 3.3V (42MX)

SM84PG-ACTEL

Abstract: A1240XL SM-10 SM68P-ACTEL SM160PQ-ACTEL SM132CQ-ACTEL A42MX36 1200XL SM176TQ-ACTEL A1010DXV
Contextual Info: Silicon Sculptor - Adapter Module Selector Guide Page 1 of 3 BACK Adapter Module Selector Guide Package Types: BG - Plastic Ball Grid Array CQ - Ceramic Quad Flat Pack PG - Ceramic Pin Grid Array PL - Plastic J-Leaded Chip Carrier Device Type A1010B A1010B