N74LS113 Search Results
N74LS113 Datasheets (4)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| N74LS113A | Unknown | TTL Data Book 1980 | Scan | 63.54KB | 1 | ||
| N74LS113N | Signetics | Dual J-K Edge-Triggered Flip-Flop | Scan | 128.51KB | 5 | ||
| N74LS113N | Signetics | Dual J-K Edge Triggered Flip-Flop | Scan | 133.69KB | 5 | ||
| N74LS113N | Signetics | Integrated Circuits Catalogue 1978/79 | Scan | 920.04KB | 27 |
N74LS113 Price and Stock
Motorola Semiconductor Products SN74LS113ANIC Flip Flop Jk-Type Neg-Edg Dual 14Pdip |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN74LS113AN | 1,046 |
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SN74LS113AN | 125 |
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Signetics N74LS113N |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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N74LS113N | 75 |
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N74LS113N | 944 |
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| N74LS113N | 75 |
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| N74LS113N | 48 |
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Texas Instruments SN74LS113ADRFlip Flop Negative Edge 2 Element 5V 14-SOIC T/R |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN74LS113ADR | 2,500 | 1 |
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Motorola Semiconductor Products SN74LS113JIN STOCK SHIP TODAY |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN74LS113J | 14 |
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Texas Instruments SN74LS113AFN3J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PQCC20 |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SN74LS113AFN3 | 9,841 |
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N74LS113 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
sr flip flop
Abstract: DN74LS113 MA161
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dn74lsdn74ls11314-pins0-140+3 | |
74LS113
Abstract: C0056
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74ls1131n9161n3064500ns+1 | |
74LS113
Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
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74ls113tr1131n9161n3064+6 | |
74LS113Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro nous Set S d input, w hen LOW, forces |
OCR Scan |
74ls1131n9161n3064500ns | |
74LS113
Abstract: S113 equivalent
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OCR Scan |
74ls113wf08450s1n9161n3064+2 | |
THERMISTORS nsp 037
Abstract: Thyristor TAG 9118 ICA 0726 0148 Transformer a1273 y k transistor AM97C11CN transistor SK A1104 PM7A2Q B8708 bzy79 yh 5032
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200x300x360mthermistors nsp 037thyristor tag 9118ica 0726 0148 transformer+7 | |
transistor cross reference
Abstract: MPT3N40 Westinghouse SCR handbook LT 8224 ZENER DIODE sje389 N9602N npn transistor RCA 467 TFK 7 segment displays PUT 2N6027 delco 466
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transistor cross referencempt3n40westinghouse scr handbooklt 8224 zener diode+6 | |
GFB7400D
Abstract: FEY101B TCA290A Rifa pmr 2026 EF184 ORP52 Mullard Mullard quick reference guide GZF1200 ITT A2610 YD 6409
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gfb7400dfey101btca290arifa pmr 2026+6 | |
transistor C3866
Abstract: Zener PH SEC E13009 ups circuit schematic diagram 1000w E13007 2 E13007 C3866 power transistor texas ttl 74L505 Transistor C3246
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transistor c3866zener phsec e13009ups circuit schematic diagram 1000w+6 | |
74LS113
Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
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OCR Scan |
74ls1131n9161n3064500ns+5 | |
74LS113Contextual Info: 74LS113, S113 Flip-Flops S ig n e tics Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION TYPE T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. T h e asynchro nous S et Sp input, when LO W , forces |
OCR Scan |
74ls113500ns1n9161n3064 |