N74LS Search Results

sr flip flop

Abstract: DN74LS113 MA161
Contextual Info: N74LS113 LS TTL N74LS Series D N 7 4 L S 1 1 3 ^ 7 ^ U S 3 Dual J-K Negative Edge-Triggered F lip -F lo p s with Set) • Description P-l D N74LS113 contains tw o negative-edge triggered J-K flip­ flop circuits, each w ith independent clock-CP, J, K, and

8253/8254

Abstract: md 8243 ITT301 6168 sc 8254 AA lt 8239 signetics B197 B236 B237
Contextual Info: Signetics Integrated C ircuits-Lo w Power Schottky T T L TYPE NO. d e s c r ip t io n STO C K NO. N74LS 260N N 74LS261N N74LS266N Dual 5 -In p u t NO R Gate M u ltip ly Decoder Quad Exclusive NOR 5S 735A 55 7 3 6 X 5 57 37H O U T L IN E DRW G. NO. 1 2 1 M 74LS273N

Contextual Info: LS TTL N74LS Series N74LS373 N74LS373 Octal D-type Transparent L a t c h e s w ith 3 -sta te Outputs • Description P-3 D N74LS373 contains eight 3-state o u tp u t D-type latch circuits w ith com m on outp u t-control enable inputs for all circuits.

74LS386

Abstract: N74LS386F N74LS386N S54LS386F S54LS386W
Contextual Info: 54LS/74LS386 ORDERING CODE PACKAGES PIN CONFIGURATION See Section 9 for further Package and Ordering Information C O M M E R C IA L RANGES ± 5%' t A = ° ° c *0 *70°c PIN CO N F. VCC = s v P lastic DIP Fig. A N74LS386N C eram ic DIP Fig. A N 74LS386F

Contextual Info: 54/7412 54LS/74LS12 ORDERING CODE PACKAGES PIN C O N F. PIN CONFIGURATION See Section 9 for further Package and Ordering Information. C O M M ERCIAL R A N G ES =5V ±5%; T a =0“C to *70"C VC C Plastic D IP Fig. A N7412N • N74LS12N Ceramic D IP Fig. A

DN74LS245

Contextual Info: N74LS245 LS TTL N74LS Series N74LS245 Octal Bus T ra n sceiv ers with 3 -s ta te Outputs H Description P-3 D N74LS245 contains eight bus transm itter/reciver circuits w ith non-inverted o utputs. /V • Features • • • • • Bidirectional transfer or separation capability for tw o 8-bit

Contextual Info: LS TTL N74LS Series N74LS109 D N 7 4 L S 1 0 9 Dual J-K Positive Edge-Triggered F lip-F lops with S et and Reset • Description P-2 D N74LS109 contains two positive-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and direct-coupled set and reset input terminals.

Contextual Info: L .o T T L N74LS08 D N 7 4 L 3 O e r ie s N74LS08 131074^? Quad 2 - input P o sitiv e AND Gates I Description P-1 D N74LS08 contains four 2-input positive isolation AND gate circuits. • Features • • • • Low power consum ption Pd = 17mW typical

74ls86n

Abstract: 74ls138n 74LS155N 74ls173n 74LS153N 74LS75N CD 8227 IC TTL 74LS153N 74LS158N 74LS161N
Contextual Info: S ig n e tic s Integrated C ircuits - Low Power S chottky T T L R EFERENCE T A B L E TYPE NO. D E S C R IP T IO N STOCK NO. N 7 4LS 51N N 7 4LS 54N N74LS 55N N 7 4LS 73N N 7 4LS 74N D u a l 2 -W id e 2 - I n p u t A O I G a te 4 -W id e 2 - I n p u t A O I G ate

74LS08 fan-out

Abstract: 74LS08 pin configuration pin configuration 74LS08 74LS 7408 7408 7408 and 7408 pin configuration specification of 74ls08 S-5408 N7408F
Contextual Info: PIN C O N F IG U R A T IO N S 54/7408 54H/74H08 54S/74S08 54LS/74LS08 ORDERING CODE I GE See Section 9 for further Package and Ordering Information. PIN CONF. P lastic DIP Fig. A Fig. A N7408N N74S08N • • N74H08N N74LS08N C era m ic DIP Fig. A Fig. A

74ls characteristics

Abstract: 74LS279 S5427 74279 truth table NOT gate 74 N74279F N74279N N74LS279F N74LS279N S54279F
Contextual Info: PIN CONFIGURATION 54/74279 54LS/74LS279 ORDERING CODE PIN CONF. PACKAGES See Section 9 for further Package and Ordering Information. C O M M ER C IA L RANGES = + 5%; T a = 0 -C to *70"C VCC Plastic DIP Fig. A N74279N • N74LS279N C eram ic DIP Fig. A N74279F

Contextual Info: I LS T T L N74LS Series N74LS74A N74LS74A Dual D -type P o sitiv e E dge-triggered F lip -F lo p s w ith S e t and R eset • Description P-1 D N74LS74A contains tw o positive-edge triggered D-type flip-flop circuits, each w ith independent clock-CP data-D,

ma161

Contextual Info: LS TTL N74LS Series N74LS112 N74LS112 Dual J-K Negative Edge-Triggered F lip-F lops with S et and Reset • P-2 Description D N74LS112 contains two negative-edge triggered J-K flip­ flop circuits, each w ith independent clock-CP, J , K, and direct-coupled set and reset in p u t term inals.

7404 NOT ic

Abstract: 7404 7404 ic pin configuration 74LS 7404 IC TTL 7404 7404 ic IC 7404 INVERTER ic 7404 maximum current IC 7404 hex inverter 7404 pin configuration
Contextual Info: 7404, LS04, S04 Signetics Inverters Hex Inverter Product Specification Logic Products TYPICAL SUPPLY CURRENT TOTAL TYPICAL PROPAGATION DELAY TYPE 7404 10ns 12mA 74LS04 9.5ns 2.4mA 74S04 3ns 22mA ORDERING CODE COMMERCIAL RANGE PACKAGES Plastic DIP N7404N, N74LS04N, N74S04N

Contextual Info: LS TTL N74LS Series N74LS83A N74LS83A \J la i s *3 r\ 4 -b it Binary Full Adders (with F ast Carry • Description P-2 D N74LS83 A is a 4-bit full-adder w ith a “ look-ahead” carry. ■ • • • Features “ Look-ahead” carry for high speed Partial “look-ahead” carry for system capability

Contextual Info: I LS TTL N74LS Series N74LS153 N74LS153 Dual 4 -lin e to 1 -lin e Data Selectors / Multiplexers • Description P-2 D N74LS153 contains tw o 4-line to 1-line data selector/ m ultiplexer circuits. ■ Features • • • • Independent enable input for each circuit

74LS386

Contextual Info: 54LS/74LS386 ORDERING CODE PIN C O N F. PACKAGES PIN CONFIGURATION See Section 9 for further Package and Ordering Information M ILITA R Y RANGES C O M M E R C IA L RANGES VCC = 5V 1 5%; Ta = 0°C lo *70°C Plastic DIP Fig. A N74LS386N Ceramic DIP Fig. A

DN74LS390

Abstract: LS290 LS90 MA161
Contextual Info: I LS TTL N74LS Series N74LS390 N74LS390 Dual Decade Counters • Description P -2 D N74LS390 contains tw o asynchronous decade counter circuits w ith direct-coupled reset inputs. ■ Features • Includes tw o circuits corresponding to LS90 and LS290 for

74L5

Contextual Info: 74LS197 Signetics Counter Presettable 4-Bit Binary Ripple Counter Product Specification Logic Products FEATURES TYPE PIN CONFIGURATION 16mA COMMERCIAL RANGE Vcc = 5V ±5%; Ta = 0°C to + 70”C PACKAGES Plastic DIP N74LS197N Plastic SO-14 N74LS197D NOTE: For information regarding devices processed to Military Specifications, see the Signetics Military Products

400M

Abstract: DN74LS155 MA161
Contextual Info: LS TTL N74LS Series D N 7 4 L S 1 5 5 i\j N74LS155 74- 15 5 Dual 2-line to 4-line Decoders/ Demultiplexers • Description P-2 D N74LS155 contains tw o 2-bit binary decoder/dem ultiplexer circuits. to quarternary ■ Features • • • • Low o u tp u t im pedance

400M

Abstract: DN74LS74A MA161
Contextual Info: I LS T T L N74LS Series N74LS74A N74LS74A Dual D -type P o sitiv e E dge-triggered F lip -F lo p s w ith S e t and R eset • Description P-1 D N74LS74A contains tw o positive-edge triggered D-type flip-flop circuits, each w ith independent clock-CP data-D,

S54LS30F

Abstract: 74LS30 N7430F N7430N N74H30F N74H30N N74LS30F N74LS30N S5430F S54H30F
Contextual Info: PIN CONFIGURATIONS 54/7430 54H/74H30 54LS/74LS30 ORDERING CODE See Section 9 for further Package and Ordering Information. C O M M E R C IA L RANGES “ 5V - 5%; T A = 0°C to *70°C PACKAGES PIN CON F. P lastic DIP Fig. A Fig. A N7430N • N74H30N N74LS30N

N7409F

Abstract: N7409N N74LS09F N74LS09N N74S09F N74S09N S5409F S54LS09F S54S09F
Contextual Info: 54/7409 54S/74S09 54LS/74LS09 ORDERING CODE PIN CONFIGURATION See Section 9 for further Package and Ordering Information. C O M M ER C IA L RANGES ± 5%; T a = 0 "C to *70°C PACKAGES PIN C O N F. P lastic DIP Fig. A Fig. A N7409N • N74S09N N74LS09N C eram ic DIP

N7401F

Abstract: N7401N N74H01F N74H01N N74LS01F N74LS01N S5401F S54H01F S54LS01F 74H01
Contextual Info: PIN CONFIGURATIONS 54/7401 54H/74H01 54LS/74LS01 ORDERING CODE See Section 9 for further Package and Ordering Information. C O M M ER C IA L RANGES VCc = sv ± 5%; T A = 0 ° C Io »7 0 °C PACKAGES PIN CONF. P lastic DIP Fig. A Fig. C N7401N • N74LS01N