MAX9310 Search Results

Contextual Info: 19-2541; Rev 0; 7/02 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs The MAX9310 is a fast, low-skew 1:5 differential driver with selectable LVPECL/HSTL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 345ps

ps1025

Abstract: MAX9310 MAX9310EUP
Contextual Info: 19-2541; Rev 0; 7/02 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs The MAX9310 is a fast, low-skew 1:5 differential driver with selectable LVPECL/HSTL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 345ps

Contextual Info: 19-2542; Rev 0; 7/02 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs The MAX9310A is a fast, low-skew 1:5 differential driver with selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. This device

GST-2

Abstract: MAX9310A
Contextual Info: MAX9310A RELIABILITY REPORT FOR MAX9310AEUP+T PLASTIC ENCAPSULATED DEVICES December 4, 2011 MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR. SUNNYVALE, CA 94086 Approved by Richard Aburano Quality Assurance Manager, Reliability Engineering Maxim Integrated Products. All rights reserved.

MAX9310A

Abstract: MAX9310AEUP
Contextual Info: 19-2542; Rev 0; 7/02 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs The MAX9310A is a fast, low-skew 1:5 differential driver with selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. This device

HDMI to vga pinout

Abstract: MAX9180 lvds 26 pin MAX9259 MAX9374 MAX9384 Video sync splitter vga SK4401 HDMI to VGA Cable diagram MAX9324
Contextual Info: High-Speed Interconnect 8th Edition February 2009 Industry’s most versatile portfolio of high-speed interface ICs Automotive SerDes for video and audio data Rear-Seat Entertainment Navigation Safety Cameras Fanout buffers, muxes, and crosspoint switches for clock and data distribution

max14574

Abstract: MAX1786 MAX1788 MAX8899 DS1849 MAX16908 MAX4967 DS3610 max17018 max13487
Contextual Info: Monitor Reports by Product: 1. Find the product of interest in the table below. Note the process and/or package for that product. 2. Use the "Back" button to return to the home page. 3. Select the process in the "Process Reliability" for the product of interest.

Si53320

Abstract: si5332
Contextual Info: Si53320 1:5 L O W J I T T E R LVPECL C LOCK B UFFER W I T H 2:1 I NPUT M UX Features         5 LVPECL outputs  Ultra-low additive jitter: 100 fs rms  Wide frequency range: 1 to 725 MHz  Input compatible with LVPECL, LVDS, CML, HCSL, LVCMOS

AN1916

Abstract: MAX9386 MAX9310 MAX9311 MAX9315 MAX9316 MAX9317 MAX9320 MAX9322 MAX9360
Contextual Info: Maxim > App Notes > HIGH-SPEED INTERCONNECT Keywords: jitter, gaussian, random, RJ, deterministic, cycle to cycle, adjacent cycle, duty cycle distortion, pulse width distortion, inter-symbol, bit error rate, BER, ber Mar 06, 2003 APPLICATION NOTE 1916 An Introduction to Jitter in Communications Systems

max9263

Abstract: MAX9259 MAX9234 DS90CR216 MAX9268 1280x480 MAX9150 max9234 MAX9257 Automotive LVDS connector LVDS 51 connector
Contextual Info: High-Speed Interconnect Product Guide Learn more Page 3mm x 3mm serializer for miniature security Gigabit, multiport, LVDS crosspoint switches minimize system

JESD86

Abstract: JESD8-6 HSTL standards MAX9310 MAX9311 MAX9312 MAX9313 MAX9314 MAX9315 MAX9316
Contextual Info: Maxim > App Notes > COMMUNICATIONS CIRCUITS Keywords: HSTL, PECL, high speed, interface standards, differential HSTL, high speed transceiver logic, Jedec standard, Jedec std, differential Sep 27, 2002 APPLICATION NOTE 1752 Applying HSTL Signals to PECL Input Devices