340PS Search Results

TC160G

Abstract: toshiba LGA Nand TC170C14 TC26SC TC170C1 TC170C29
Contextual Info: TOSHIBA TC170C CMOS Standard Cell 0.7\xm , 5.0V ASICs The 0.7nm, 5V TC170C allows higher area efficiency, system performance and device integration with lower power than previous generation 5V standard cell products Benefits • Advanced 0.7 micron CMOS process with fast 250ps gate

SY58021U

Abstract: SY89854U SY89854UMG SY89854UMGTR
Contextual Info: SY89854U Precision Low Power 1:4 LVPECL Fanout Buffer/Translator with Internal Termination General Description The SY89854U is a 2.5V/3.3V precision, highspeed, fully differential 1:4 LVPECL fanout buffer. Optimized to provide four identical output copies

SY58028U

Abstract: SY58029U SY58030U SY58030UMG SY58030UMGTR SY58030UMI SY58030UMITR
Contextual Info: Precision Edge ULTRA PRECISION, 400mV SY58030U ® DIFFERENTIAL LVPECL 4:1 MUX with 1:2 Precision Edge SY58030U FANOUT and INTERNAL TERMINATION Micrel, Inc. FEATURES „ Selects 1 of 4 differential inputs „ Provides two copies of the selected input „ Guaranteed AC performance over temperature and

pmi op50

Abstract: ic PMI OP50 OP-50 OP-50AY OP-50EY OP50 0P-50
Contextual Info: High-Output-Current Operational Amplifier A^ > 5 0P-50 ANALOG DEVICES □ FEATU RES • Open-Loop G a in . . . 10.000.000V/V Min • Low Input onset Voltage _ . 25MV Max • Low Input Mas Current. • ExeeHent TCVo«. .Q.3*iV/°C Max

DL140

Abstract: MC100EL05 MC100LVEL05 LVEL05
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2ĆInput Differential AND/NAND MC100LVEL05 The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3V supply voltage. With propagation delays and output transition

Contextual Info: Low phase noise, Dual 1-to-6, 3.3V, 2.5V LVPECL Output Fanout Buffer IDT8SLVP2106I DATASHEET General Description Features The IDT8SLVP2106I is a high-performance differential dual 1:6 LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.

ICS951601

Contextual Info: ICS951601 Integrated Circuit Systems, Inc. Preliminary Product Preview General Purpose Frequency Timing Generator Recommended Application: General Purpose Clock Generator Output Features: • 17 - PCI clocks selectable, either 33.33MHz or 66.6MHz @ 3.3V • 1 - 48MHz @ 3.3V

ICS951601

Contextual Info: ICS951601 Integrated Circuit Systems, Inc. Preliminary Product Preview General Purpose Frequency Timing Generator Key Specifications: • PCI – PCI output skew within same bank @ 33MHz: <170ps Output Features: • 17 - PCI clocks selectable, either 33.33MHz or 66.6MHz @ 3.3V

Contextual Info: Precision Edge ULTRA PRECISION, 400mV SY58030U ® DIFFERENTIAL LVPECL 4:1 MUX with 1:2 Precision Edge SY58030U FANOUT and INTERNAL TERMINATION Micrel, Inc. FEATURES • Selects 1 of 4 differential inputs ■ Provides two copies of the selected input ■ Guaranteed AC performance over temperature and

W83195CG

Abstract: W83195CG-920
Contextual Info: W83195CG-920 Winbond Clock Generator with DDR I/II Buffer For VIA P4 Series Chipset Date: Apr/10/2006 Revision: 0.6 W83195CG-920 CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET W83195CG-920 Data Sheet Revision History PAGES DATES VERSION WEB VERSION

PD65625

Abstract: PD65654 V30MZC PD65808 V30MX PD65875 PD65842 PD65841 CMOS-N5 PD65802
Contextual Info: CD-ROM版セミカスタム IC CD-ROM X13769XJ2V0CD00 05−1 セミカスタム IC NECのASIC • ASICとは？（1/2） LSIは大きく，汎用LSIと特定用途向けLSI （ASIC：Application Specific IC） とに分けられます。 汎用LSIは， メーカ側で独自に設計し標準のLSIとして市販されているLSIです。各ユーザの使用量は少なくても大

Contextual Info: SY89851U Low Power, 3GHz, 1:2 LVPECL Fanout Buffer/Translator with Internal Termination General Description The SY89851U is a low jitter, low skew, high-speed 1:2 differential fanout buffer optimized for precision telecom and enterprise server distribution

Contextual Info: SY89852U Precision Low Power Differential 2:1 LVPECL MUX with Internal Termination General Description The SY89852U is a 2.5V/3.3V precision, highspeed, 2:1 differential MUX capable of handling clocks up to 2.5GHz and data streams up to 2.5Gbps. The differential input includes Micrel’s unique, patent

Contextual Info: SY89854U Precision Low Power 1:4 LVPECL Fanout Buffer/Translator with Internal Termination General Description The SY89854U is a 2.5V/3.3V precision, highspeed, fully differential 1:4 LVPECL fanout buffer. Optimized to provide four identical output copies

48MHZ

Abstract: 72MHZ SEL24 W83194BR-PT
Contextual Info: W83194BR-PT WINBOND STEPLESS VIA PT MAIN CLOCK GENERATOR -I- Publication Release Date:April 13, 2005 Revision 1.1 W83194BR-PT Table of Contents1. GENERAL DESCRIPTION . 1

Contextual Info: SY89854U Precision Low Power 1:4 LVPECL Fanout Buffer/Translator with Internal Termination General Description The SY89854U is a 2.5V/3.3V precision, highspeed, fully differential 1:4 LVPECL fanout buffer. Optimized to provide four identical output copies

Contextual Info: 19-2542; Rev 0; 7/02 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs The MAX9310A is a fast, low-skew 1:5 differential driver with selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. This device

SY58021U

Abstract: SY89854U SY89854UMG SY89854UMGTR
Contextual Info: SY89854U Precision Low Power 1:4 LVPECL Fanout Buffer/Translator with Internal Termination General Description The SY89854U is a 2.5V/3.3V precision, highspeed, fully differential 1:4 LVPECL fanout buffer. Optimized to provide four identical output copies

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2 -ln p u t D iffe re n tia l A N D /N A N D M C 100LVEL05 The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3V supply voltage. With propagation delays and output transition

W83195BR-341

Abstract: SEL24 W83195BG-341 SA5861
Contextual Info: W83195BR-341 W83195BG-341 WINBOND CLOCK GENERATOR FOR VIA P4/KT SERIES CHIPSET Date: Mar/21/2006 Revision: 1.1 W83195BR-341/W83195BG-341 CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET W83195BR-341/W83195BG-341 Data Sheet Revision History PAGES DATES VERSION WEB VERSION

W83194BR

Abstract: DD48 SEL24 W83194BR-372 Analog devices TOP marking Information ref0
Contextual Info: W83194BR-372 WINBOND CLOCK GENERATOR FOR SIS 746/748 CHIPSETS -I- Publication Release Date: December 28, 2004 Revision 1.0 W83194BR-372 Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS All of the versions before 0.50 are for internal use. 1 2

M9999-071205

Contextual Info: SY89851U Low Power, 3GHz, 1:2 LVPECL Fanout Buffer/Translator with Internal Termination General Description The SY89851U is a low jitter, low skew, high-speed 1:2 differential fanout buffer optimized for precision telecom and enterprise server distribution

W83195CG

Abstract: W83195CG-920 DSA0091627
Contextual Info: W83195CG-920 Winbond Clock Generator with DDR I/II Buffer For VIA P4 Series Chipset Date: Apr/10/2006 Revision: 0.6 W83195CG-920 CLOCK GEN. with DDRI/II Buffer For VIA P4 SERIES CHIPSET W83195CG-920 Data Sheet Revision History PAGES DATES VERSION WEB VERSION

w83194br

Contextual Info: W83194BR-903 & W83194BG-903 STEPLESS VIA PT/PM MAIN CLOCK GENERATOR Date: 5/2/2006 Revision: 1.0 W83194BR-903/W83194BG-903 W83194BR-903 Datasheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS n.a. All of the versions before 0.50 are for internal