DL140 Search Results

E142 wafer format

Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Contextual Info: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved”

Contextual Info: High Performance ECL Data ECLinPSt and ECLinPS Litet DL140/D Rev. 7, January−2005  SCILLC, 2005 Previous Edition  2001 “All Rights Reserved’’ http://onsemi.com 1 ECLinPS and ECLinPS Liite are trademarks of Semiconductor Components Industries, LLC

nippon capacitors

Abstract: DL140 MC100E336 MC10E336
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit Registered Bus Transceiver MC10E336 MC100E336 The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs BUS0–BUS2 are specified for driving a 25Ω bus; the receive outputs (Q0 – Q2) are

DL140

Abstract: VCO 100mhz SC931
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Customer Specific Semiconductor SC931 Low Voltage PLL Clock Driver The SC931 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock applications. With output frequencies of up to 140MHz and output skews of 300ps the SC931 is ideal for the most demanding clock distribution designs.

948F

Abstract: DL140 MC10SX1127 MECL10H
Contextual Info: MOTOROLA Order this document by MC10SX1127/D SEMICONDUCTOR TECHNICAL DATA Product Preview MC10SX1127 2.5Gb/s Fiber Optic Post Amplifier The MC10SX1127 is an integrated limiting amplifier for high frequency fiber optic applications. The device interfaces directly to the

MPC2510

Abstract: DL140 MPC953
Contextual Info: MOTOROLA Order this document by MPC2510/D SEMICONDUCTOR TECHNICAL DATA Product Preview MPC2510 Low Voltage PLL Clock Driver The MPC2510 is a 3.3V compatible, PLL based zero delay buffer targeted for high performance clock tree designs. With 11 outputs at frequencies of up to 125MHz and output skews of 200ps the MPC2510 is

nippon capacitors

Abstract: DL140 E336 MC100E337 MC10E337
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit Scannable Registered Bus Transceiver The MC10E/100E337 is a 3-bit registered bus transceiver with scan. The bus outputs BUS0–BUS2 are specified for driving a 25Ω bus; the receive outputs (Q0 – Q2) are specified for 50Ω. The bus outputs feature

AN1091

Abstract: AN1545 DL140 MPC953
Contextual Info: MOTOROLA Order this document by MPC953/D SEMICONDUCTOR TECHNICAL DATA MPC953 Low Voltage PLL Clock Driver The MPC953 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 110MHz and output skews of 150ps the MPC953 is ideal for the

DL140

Abstract: E210 LVE111 MC100E210 MC100LVE210
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer MC100LVE210 MC100E210 ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features

DL140

Abstract: MC100EL05 MC100LVEL05 LVEL05
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2ĆInput Differential AND/NAND MC100LVEL05 The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3V supply voltage. With propagation delays and output transition

DL140

Abstract: MC100LVEL37
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 1:4 ÷1/÷2 MC100LVEL37 ECL/PECL Clock Fanout Buffer The MC100LVEL37 is a fully differential 1:4 fanout buffer. The device offers two outputs at ÷1 of the input frequrency, and two outputs at ÷2 of the input frequency. The Low Output–Output Skew of the device makes it

751D-04

Abstract: DL140 MC100EL59 MC100LVEL59 DM 1265
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple 2:1 Multiplexer MC100LVEL59 MC100EL59 The MC100LVEL59 is a triple 2:1 multiplexer with differential outputs. The MC100EL59 is pin and functionally equivalent to the MC100LVEL59 but is specified for operation at the standard 100E ECL voltage supply.

LVELT23

Abstract: DL140 MC100LVELT23
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Dual Differential LVPECL to MC100LVELT23 TTL Translator The MC100LVELT23 is a dual differential LVPECL to TTL translator. Because LVPECL Positive ECL levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate

pdc 140

Abstract: DL140 E195 MC100E195 MC10E195
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 MC100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.

DL140

Abstract: LVEL16 MC100LVEL16
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Differential Receiver MC100LVEL16 The MC100LVEL16 is a differential receiver. The device is functionally equivalent to the EL16 device, operating from a low voltage supply. The LVEL16 exhibits a wider CMR range than its EL16 counterpart. With

DL140

Abstract: E195 MC100E195 MC10E195
Contextual Info: MOTOROLA Order this document by MC10E195/D SEMICONDUCTOR TECHNICAL DATA MC10E195 MC100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.

Motorola, Inc. identical in pinout to

Abstract: DL140 MC100E171 MC10E171
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit 4:1 Multiplexer MC10E171 MC100E171 The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . The three Select inputs control which one of the

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA P roduct Preview MC100LVEL32 ^-2 Divider The MC100LVEL32 is an integrated +2 divider. The differential clock inputs and the V b b allow a differential, single-ended or AC coupled interface to the device. If used, the V b b output should be bypassed to

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA ^4 Divider MC10EL33 MC100EL33 The MC10EL/100EL33 is an integrated +4 divider. The differential clock inputs and the V b b allow a differential, single-ended or AC coupled interface to the device. If used, the V b b output should be bypassed to ground with a

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Differential Receiver MC10EL16 MC100EL16 The MC10EL7100EL16 is a differential receiver. The device is functionally equivalent to the E116 device with higher performance capabilities. With output transition times significantly faster than the E116

Contextual Info: M OTOROLA SEMICONDUCTOR TECHNICAL DATA TTL to Differential PECL Translator MC10ELT20 MC100ELT20 The MC10ELT/100ELT20 is a TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 M C100E195 Program m able Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay ot a differential ECL input transition.

Contextual Info: M O TO RO LA SEMICONDUCTOR TECHNICAL DATA Low Voltage 1:2 Differential Fanout Buffer The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times

Contextual Info: M OTOROLA SEMICONDUCTOR TECHNICAL DATA Differential PECL to TTL Translator MC10ELT21 MC100ELT21 The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of