LS109A Search Results

Contextual Info: LS109A National Semiconductor 54LS109/LS109A/DM74LSJ09A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

TTL 74109

Abstract: PIN CONFIGURATION 74109 853051 8530510 74LS109A
Contextual Info: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also com­ plementary Q and 5 outputs.

SN54ALS109A

Abstract: SN54AS109 SN74ALS109A
Contextual Info: SN 54A LS109A , SN 54A S109i_SN 74A LS109A . SN 74A S109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP FLOPS WITH CLEAR AND P R ESET D 2 6 6 1 . A P R IL 1 9 8 2 - SN 54A LS109A , SN 54A S109 . . . J PACKAG E S N 7 4 A L S 1 0 9 A . S N 7 4 A S 1 0 9 . . D OR N P A C K A G E

TTL 74109

Abstract: 8530510 74109 PIN CONFIGURATION 74109
Contextual Info: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 0 9 is dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, S e t and R eset inputs; also com ­

54LS109

Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AN J16A M16A LS109 DM74LS109
Contextual Info: LS109A National Semiconductor 54LS109/LS109A/LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and

pin diagram of 74109

Abstract: 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A
Contextual Info: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74109 33MHz 9mA LS109A 33MHz 4mA DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K,

74HC4096

Abstract: EQUIVALENT TIMER IC WITH CD 4060 rs flip-flop IC 7400 C4050A shiftregister PIPO C148A LS 7476 L1AA C4051A LS294
Contextual Info: Selection Guide C2MOS Logic TC74HC/HCT Series 2. High Speed CMOS Selection Guide GATE NAND HCOOA NOR AND OR INVERTER, BUFFER EXCLUSIVE OR/NOR SC HM ITT TRIGGER HC02A HC08A H C31A H C04A H C86A H C14A H C51A H C4049A M ULTI FUNCTION LEVEL SHIFTER HCTOOA HCT02A

LS109A

Contextual Info: AVG Semiconductors DDi Technical Data 109 A Dual JK Positive Edge-Triggered Flip-Flops LS109A LS109A This device is_a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, reset and preset inputs, and also com­ plementary Q and Q outputs.

SN74109

Abstract: LS109A SN54109 SN54LS109A SN74 SN74LS109A rv101
Contextual Info: SN54109, LS109A, SN74109, LS109A d u a l j k p o sitiv e e d ge -trigge re d flip -flo p s w ith p re se t and c le a r s d l s 037 DECEMBER 1 9 8 3 - • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

JM38510/01405BEA

Abstract: M38510
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) JM38510/30109B2A ACTIVE LCCC

74AS109

Contextual Info: LS109A, SN54AS109, LS109A, SN74AS109 DUAL J K POSITIVE EDGE TRIGGERED FLIP FLOPS WITH CLEAR AND PRESET D 2 6 6 1 , A P R IL 1 9 8 2 - S N 5 4 A L S <09A, S N 5 4 A S 1 0 9 . . . J P A C K A G E SN 7 4 A LS 1 0 9 A . SN 74A S 109 . . , D OR N P ACKAG E

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

Contextual Info: Z9A National SLA Semiconductor 54LS109/LS109A/DM74LSJI09A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and

Contextual Info: SG60R4 Schottky TTL • Over 180 LS Devices • ALS • FAST TOTAL TTL COMMITMENT «TOTAL • TTL Compatible Macrocell Arrays • RAMs • PROMs General Information TTL in Perspective proved speed — p o w e r product co m p ared to LS as a result o f ad vanced M O S A IC oxide isolated processing.

mc68701 probug

Abstract: MC144100 M68KVM02 user manual m6809 EXORCISER motorola MC146805G2 MC1468705G2 AN/mc68701 probug
Contextual Info: Motorola’s Microcomputer Families i Reliability Data Sheets Mechanical Data E Technical Training Memory Products Logic and Special Function Products Development Systems and Board-Level Products E M motorola MICROCOMPUTERS Prepared by Technical Information Center

Contextual Info: Philips Sem iconductors Product specification 7A. Q1flQ. Dual J-K positive edge triggered flip-flop with set and reset PIN CONFIGURATION DESCRIPTION The LS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and

0PIC

Abstract: LS66 SN74L30 84LS 64LS 84ls AX-2016 MAX2719 hy74 L8128A SN7463
Contextual Info: V 84 F A M IL Y S E R IE S 54 S E R IE S M L S S E R IE S B4S S E R IE S 74 S E R IE S 54H S E R IE S 74H S E R IE S 5 4 L 74 F A M IL Y S E R IE S 7 4 L S E R IE S 7 4 LS S E R IE S 74S *00. *04, *H 0 0 ,1404. *L00, 'U M , XSOO, *100, *S04, '10. *20, *30

LG color tv Circuit Diagram schematics

Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
Contextual Info: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS

ic 74 LS 138 DECODER

Abstract: Alu 181 8 bit bcd adder/subtractor f245 motorola lal 2084 TTL 74-series IC LIST internal circuitry for sr flip flop T flip flop IC LS248 4-bit bcd subtractor
Contextual Info: SG 6 0R 4 Schottky TTL • O v e r 180 LS Devices • ALS • FAST • TTL C o m p a tib le M acrocell A rra y s • RAMs • PR O M s 006844 /y err This Material Copyrighted By Its Respective Manufacturer General Inform ation TTL in Perspective proved speed — p o w e r product co m p ared to LS as a

LS109A

Abstract: ALS109A
Contextual Info: A VG Semiconductors DDT Technical Data LS109A LS109A This device is_a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, reset and preset inputs, and also com­ plementary Q and Q outputs. Information at input J or K is transferred to the Q output on the

MA116

Abstract: pin diagram of 74109
Contextual Info: SN54109, LS109A, SN74109, LS109A DUAL J K POSITIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR D ECEM BER 1983 - Package Options Include Plastic "Sm all O utline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs S N 5 4 1 0 9 , S N 5 4 L S 1 0 9 A . . . J OR W PACKAGE

1u9a

Contextual Info: Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset DESCRIPTION PIN CONFIGURATION The LS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and

S691 oscillator

Abstract: 74hc 4514 ap HC4078 HC592A 4017 timer ic HC593A S688 LS194A HC165A 4017 Decade Counter IC
Contextual Info: 2. HIGH SPEED CMOS SELECTION GUIDE NAND NOR AND OR INVERTER,BUFFER EXCLUSIVE OR/NOR SCHMITT TRIGGER MULTI FUNCTION LEVEL SHIFTER RTIQ RlIFPfT} HCOOA HCTOOA HC03A HC10A HC20A HC30A HC132A HC133A HC02A HCT02A HC27A HC4002A HC4078A HC08A HCT08A HC09A HCUA HC21A

pin diagram of 74109

Abstract: 74109 PIN CONFIGURATION 74109 74109 dual JK TTL 74109 N74LS109AN ttl 74ls109 74LS109A LS109A 1N3064
Contextual Info: 7 4 1 0 9 , LS1 0 9 A Flip-Flops S ig n e t ic s Dual J-K P ositive Edge-Triggered Flip-Flop Product Specification Logic P rod ucts DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also com­