CY7C157 Search Results

Contextual Info: CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

CY7C1570KV18

Contextual Info: CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

Contextual Info: CY7C1568XV18, CY7C1570XV18 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36)

CY7C157

Contextual Info: CY7C157 — 16,384 x 16 Static R/W RAM S'"Os CYPRESS SEMICONDUCTOR F eatu res F u n ctio n al D escrip tio n • O p tim ized fo r use w ith CY 7C600 SPARC p ro d u c t fam ily T h e CY 7C157 is a high-perform ance C M O S static R A M organized as 16,384 x

CY7C1565V18

Abstract: CY7C1563V18 CY7C1563V18-400BZXC CY7C1563V18-400BZC CY7C1561V18 CY7C1576V18 CY7C1565V18-400BZC
Contextual Info: CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 72-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 400 MHz clock for high bandwidth

ecn 1310

Contextual Info: CY7C1561KV18, CY7C1576KV18 CY7C1563KV18, CY7C1565KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:

3M Touch Systems

Contextual Info: CY7C1568XV18, CY7C1570XV18 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36)

j6920

Abstract: CY7C600
Contextual Info: CYPRESS SEMICONDUCTOR MbE D O SSÔTbbS □□□bLf33 S Z I CYP v CYPRESS -­ SEMICONDUCTOR CY7C157A 16,384 x 16 Static R/W Cache Storage Unit Features Ebnctional Description • Optimized for use with RISC proces­ sors, Including SPARC • Address and WE registers

CY7C157A

Contextual Info: CY7C157A 16,384 x 16 Static R/W Cache Storage Unit PRELIMINARY CYPRESS _ SEMICONDUCTOR Features • Optimized for use with CY7C600 SPARC product family • Address and WE registers • CMOS for optimum speed/power • High speed - 2 0 ns • Data In and Data Out latches

phase sequence indicator

Abstract: CY7C1565V18 CY7C1561V18 CY7C1563V18 CY7C1576V18
Contextual Info: CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 72-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:

3M Touch Systems

Abstract: CY7C1570KV18
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (8 M x 8, 8 M × 9, 4 M × 18, 2 M × 36)

3M Touch Systems

Contextual Info: CY7C1568XV18, CY7C1570XV18 72-Mbit DDR II+ Xtreme SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

ecn 1310

Abstract: CY7C1565KV18-400BZI 3M Touch Systems
Contextual Info: CY7C1561KV18, CY7C1576KV18 CY7C1563KV18, CY7C1565KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:

Contextual Info: CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

Contextual Info: CY7C1568V18 CY7C1570V18 PRELIMINARY 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 72-Mbit density (4M x 18, 2M x 36) 300 MHz to 400 MHz clock for high bandwidth 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1577V18 CY7C1568V18 CY7C1570V18 PRELIMINARY 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 72-Mbit density (8M x 9, 4M x 18, 2M x 36) • 300 MHz to 400 MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: CY7C1568XV18/CY7C1570XV18 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

CY7C1568KV18

Abstract: CY7C1570KV18 78 ball fbga thermal resistance
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • 72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36) With Read Cycle Latency of 2.5 cycles: ■ 550 MHz Clock for High Bandwidth

ecn 1310

Contextual Info: CY7C1561KV18, CY7C1576KV18 CY7C1563KV18, CY7C1565KV18 PRELIMINARY 72-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:

3M Touch Systems

Contextual Info: CY7C1568XV18, CY7C1570XV18 72-Mbit DDR II+ Xtreme SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:

CY7C1568KV18

Abstract: CY7C1570KV18 3M Touch Systems
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (8 M x 8, 8 M × 9, 4 M × 18, 2 M × 36)

CY7C169

Abstract: 54600
Contextual Info: Thermal Management CYPRESS Part Number CY7B173 CY7B174 CY7B180 CY7B181 CY7B185 CY7B186 CY7B191 CY7B192 CY7B194 CY7C122 CY7C123 CY7C128 CY7C128A CY7C130 CY7C131 CY7C132 CY7C136 CY7C140 CY7C141 CY7C142 CY7C146 CY7C147 CY7C148 CY7C149 CY7C150 CY7C157 CY7C161A

7C602

Abstract: CY7C601
Contextual Info: CY7C602A CYPRESS SEMICONDUCTOR Features • Direct interface to CY7C601 integer unit • Direct interface to CY7C157 Cache Storage Unit CSU • FullcompliancewithANSI/IEEE-754 standard for binary floating-point arithmetic • Supports single and double precision

3M Touch Systems

Contextual Info: CY7C1561KV18 CY7C1576KV18 CY7C1565KV18 72-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports