960SX Search Results
960SX Price and Stock
MPE-Garry GmbH 088-3-096-0-S-XS0-0870Connector: pin strips; socket; male; data; PIN: 96; THT; angled; 3x32 |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
088-3-096-0-S-XS0-0870 | 5,000 |
|
Get Quote | |||||||
MPE-Garry GmbH 088-3-096-0-S-XS0-1590Connector: pin strips; socket; male; data; PIN: 96; THT; angled; 3x32 |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
088-3-096-0-S-XS0-1590 | 5,000 |
|
Get Quote | |||||||
MPE-Garry GmbH 088-3-096-0-S-XS0-0740Connector: pin strips; socket; male; data; PIN: 96; THT; angled; 3x32 |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
088-3-096-0-S-XS0-0740 | 5,000 |
|
Get Quote | |||||||
MPE-Garry GmbH 088-3-096-0-S-XS0-1770Connector: pin strips; socket; male; data; PIN: 96; THT; angled; 3x32 |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
088-3-096-0-S-XS0-1770 | 5,000 |
|
Get Quote | |||||||
MPE-Garry GmbH 088-3-096-0-S-XS0-1890Connector: pin strips; socket; male; data; PIN: 96; THT; angled; 3x32 |
|||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
088-3-096-0-S-XS0-1890 | 5,000 |
|
Get Quote | |||||||
960SX Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
|
Contextual Info: V960PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR ¡960 Sx PROCESSORS • Glueless interface between Intel ¡960Sx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation • Up to 1 Kbyte burst access support on both local |
OCR Scan |
v960pbc960sx8/16-bitlad24+1 | |
V96SSC25LPContextual Info: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller |
OCR Scan |
v96ssc25mhz100-pini960sx+6 | |
i960JContextual Info: V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS Glueless interface to Intel’s ¡960Jx and IBM’s PowerPC 401 Gx processors Configurable for primary master, bus master or target operation. On-the-fly byte order endian conversion |
OCR Scan |
v350epc960jx640-byte64-byte+3 | |
|
Contextual Info: ÿ y : V96SSC Rev. B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to 960Sx/Jx and PPC401 Gx processors • High-perform ance burst DRAM controller • Two-channel fly-by DMA controller • Serial com m unications unit |
OCR Scan |
v96ssci960sx/jxppc4018/16-bit+6 | |
V360EPC
Abstract: 1gg7 Extended Sector Remapper V3 Semiconductor V350EPC design of dma controller using vhdl eeprom programmer schematic 24c02 V292PBC V960PBC V961PBC
|
OCR Scan |
am29k960/am29kv350epcv96ssc+9 | |
PJ3NContextual Info: . . y lf • * ▼ • =1004200 0 0 0 0 0 2 1 V96DPC f « 450 ■ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx/Jx/Sx AND PowerPC 40lGx PROCESSORS • Glueless interface between 960Sx/Jx/Cx/Hx, PPC401 Gx processors and two PCI buses • On-the-fly byte order endian conversion |
OCR Scan |
v96dpc40lgxi960sx/jx/cx/hxppc401+7 | |
PPC401
Abstract: MAS 10 RCD V3 SEMICONDUCTOR I960SA V96SSC AV9154-04
|
OCR Scan |
v96ssc960jx960sxppc401+4 | |
|
Contextual Info: Chapter 1 Introduction In a very short period of tim e the PCI bus standard has moved beyond the PC to become the most w idely accepted high-perform ance bus standard for embedded applications. As a leader in providing chipset solutions for high-end embedded applications, V3 Sem iconductor |
OCR Scan |
am29k960/am29kv350epcpin91+1 | |
symbios
Abstract: 53c770 DAC960SX bbu installation NCR SCSI CHN 747 display lcd driver controller database chn 745 Rbl 69 DAC960
|
Original |
dac960sxsymbios53c770bbu installation+6 | |
|
Contextual Info: •iOONSna 0 0 0 0 0 4 7 V960PBC V 313 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Sx PROCESSORS “ • Glueless interface between ¡960Sx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n architecture |
OCR Scan |
v960pbc960sx576-byte33mhz+4 | |
STKK
Abstract: tvp ul 137 AD12 AD14 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
|
OCR Scan |
v350epc960jx/sx640-byte64-byte+13 | |
|
Contextual Info: v* * -m am # if A V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS T „v * '« IC O * 1Glueless ¡960Jx/Sx processors interface 1120 ready hardware messaging unit 1Large, 640-byte FIFOs using V3’s unique D y n a m ic B a n d w i d t h A l l o c a t i o n architecture |
OCR Scan |
v350epc960jx/sx640-byte64-byte+1 | |
|
Contextual Info: Chapter 1 Introduction to the V96SSC The V96SSC High-lntegration System Controller provides many of the common peripheral functions required to build a high-perform ance ¡960 Sx or ¡960Jx processor based system in one low-cost component. The V96SSC coupled with DRAM, ROM, and one of Intel’s |
OCR Scan |
v96ssc960jx960sxppc401 |