1N4002
Abstract: 80960CF 80960Cx
Contextual Info: Designing for 80960Cx and 80960Hx Compatibility Application Note December 1997 Order Number: 272556-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
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8510H
Abstract: i960 Cx Processor Instruction Set Quick Reference 80960CA AP-716 MCON00
Contextual Info: A AP-716 APPLICATION NOTE 80960Cx/80960Jx/80960Hx Architectural Comparison Tom Johnson SPG 80960 Systems Engineer Intel Corporation Mail Stop CH6-311 5000 W. Chandler Blvd. Chandler, Arizona 85226 January 29, 1996 Order Number: 272694-001 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability
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D8905
Abstract: "printer controller"
Contextual Info: PRINTERS DESTINY TECHNOLOGY CORPORATION D8905 Page Printer Coprocessor • ■ ■ ■ ■ ■ ■ ■ ■ ■ Optimized For Intel i960 Processor Family 40960Sx, 80960Kx, 80960Cx Programmable Wait States For Various Memory and I/O Devices Supports Interleave Memory
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va80960ca25
Abstract: va80960 de sw033 80960CA 80960CF 80960CF-40 A20A
Contextual Info: 80960Cx Processor Specification Update October 1998 Notice: The 80960Cx processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
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Intel AP-506
Abstract: 811 D17 031 TRANSISTOR i960HA
Contextual Info: intei AP-506 APPLICATION NOTE Designing for 80960Cx and 80960Hx Compatibility March 1995 I 1-433 AP-506 INTRODUCTION The 80960HA/HD/HT^ processors, Intel’s new superscalar i960 processor, adds new features and performance to the other well-known products in the i960 processor family. The 80960Hx
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1N4002
Abstract: 80960CF 272556 AP-505
Contextual Info: A LITERATURE CHANGE NOTICE SEMICONDUCTOR PRODUCTS DIVISION - 80960 Subject:Updates for AP-506, Designing for 80960Cx and 80960Hx Compatibility Intel literature number 272556-001 18 October 1995 Dear Customer: Thank you for ordering the Applications Note AP-506, Designing for 80960Cx and 80960Hx
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272484
Abstract: A2Y 4h 80960MX
Contextual Info: in t J AP-716 APPLICATION NOTE 80960Cx/80960Jx/80960Hx Architectural Comparison January 29, 1996 Order Number: 272694-001 1-607 in y 1.0 AP-716 Introduction This document describes three implementations of the i960 architecture: the 80960Cx, 80960Jx, and 80960Hx
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transistor 778
Abstract: cpu 80960kx printer controller 80960SX Destiny d5001 D8905
Contextual Info: PRINTERS DESTINY TECHNOLOGY CORPORATION D5001 Page Printer Coprocessor • ■ ■ ■ ■ ■ ■ ■ ■ ■ Optimized For Intel i960 Processor Family 80960Sx, 80960Kx, 80960Jx and 80960Cx Supports Up to 1200 dpi Resolutions Band Processing Requires Less
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i960 Cx Instruction Set Quick Reference
Abstract: i960 Cx Processor Instruction Set Quick Reference 80960CA de sw033 SV908 80960CA-33 80960CF 80960CF-40 A20A SW147
Contextual Info: 80960Cx Processor Specification Update August 2004 Notice: The 80960Cx processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
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VA80960CA25
Abstract: i960 Cx Instruction Set Quick Reference SV914 80960CA 80960CF 80960CF-40 A20A 272875
Contextual Info: 80960Cx Processor Specification Update April 1998 Notice: The name of product may contain design defects or errors known as errata which may cause the 80960Cx processors’ behavior to deviate from published specifications. Current characterized errata are documented in this specification update.
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Contextual Info: irrtel LITERATURE CHANGE NOTICE SEMICONDUCTOR PRODUCTS DIVISION - 80960 Subject: Updates for AP-506, Designing for 80960Cx and 80960Hx Compatibility Intel literature number 272556-001 18 October 1995 Dear Customer: Thank you for ordering the Applications Note AP-506, Designing for 80960Cx and 80960Hx
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MPPC 001
Abstract: MPPC 001 ci mppc CADDR15 9711S 9711PT4
Contextual Info: 9711 Data Compression Processor Hi/fnTM supplies two of the Internet’s most important raw materials: compression and encryption. Hi/fn is also the world’s first company to put both on a single chip, creating a processor that performs compression and encryption at
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LA3101
Abstract: PC19060 Igus LD-310 LDL8 pci9080 80960Cx 93C06 I960CX NM93CS06
Contextual Info: PCI 9060 T E C December, 1995 VERSION 1.2 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General D escrip tio n _ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local
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Contextual Info: [PIM2>[E U T P^E^OO in te i 80960HA/HD/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Binary Compatible with Other80960 Processors • Two Instructions/Clock Sustained Execution 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers
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Contextual Info: 80960CF-40 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining
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micro instruction set of I960 hx
Abstract: 80960CA 80960CF 80960HA 80960HD 80960HT 80960JA Intel i960
Contextual Info: Intel i960® Processors i960® Architecture Family Product Highlights • 32-bit register-based RISC core in all processors ■ Code compatibility across entire product line ■ Broad selection of price and performance levels ■ Ideal for networking and imaging
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Non-Pipelined processor
Abstract: 80960CF 80960CA intel packaging handbook 240800 80960CF-33 80960CF-40 Non-Pipelined Single-Cycle processor 270710
Contextual Info: A PRELIMINARY 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR • ■ ■ ■ ■ ■ • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining
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Contextual Info: PCI 9060 December, 1995 PCI Bus Master Interface Chip for VERSION 1.2 Adapters and Embedded Systems Features • • • • • • • • General Description _
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Non-Pipelined processor
Abstract: 80960HA 80960HD 80960HT A80960HT60 272495
Contextual Info: 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Datasheet Product Features • ■ ■ ■ ■ ■ 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers — 1.28 Gbyte Internal Bandwidth
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i960 KB Processor
Abstract: Pic PID control code 80960RP MON960
Contextual Info: i960 Processor Library Supplement Order Number: 651231-002 Revision Revision History Date -001 Original Issue. 02/96 -002 Revised for Release 5.1. 01/97 In the United States, additional copies of this manual or other Intel literature may be obtained by writing:
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80960HT
Abstract: 80960HA 80960HD 272495 D1365 D2962 2xcore
Contextual Info: ADVANCE INFORMATION 80960HA/HD/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • 32-Bit Parallel Architecture ■ 3.3 V Supply Voltage — — — — Load/Store Architecture Sixteen 32-Bit Global Registers Sixteen 32-Bit Local Registers 1.2 Gbyte Internal Bandwidth
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MC 9080
Abstract: hp image point hx 210830 EP80960 auto changing in/out indicator doorbell project i960 MC Programmers Reference Manual MON960 seven segment quad digit display red input pci9080 53c87
Contextual Info: MON960 Debug Monitor User’s Guide Order Number: 484290-008 Revision Revision History Date -001 Original Issue. 01/93 -002 Updated for V1.1 release. 02/93 -003 Revised for MON960 release 2.0. 05/94 -004 Revised for MON960 release 2.1. 11/94 -005 Revised for MON960 release 3.0.
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i960CA
Abstract: ka 20885 D 80960 EP80960BB atu-3 FF90FF i960 KA/KB Programmers Reference Manual 80960CF 80960RP IQ80960RP
Contextual Info: Getting Started with the 80960 QUICKval Kit i960 Microprocessor Evaluation Kit Order Number: 632708-005 Revision Revision History Date -001 Original Issue. 12/94 -002 80960Hx and PCI80960DP chapters added. Additional examples for all processors added. 12/95
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Contextual Info: PCI 9060SD MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters General Description _ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and slave adapters
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