7C10925 Search Results

Contextual Info: fax id: 1047 CY7C109 CY7C1009 ^C YPR ESS 128K x 8 Static RAM active HIGH chip enable CE 2 , an active LOW output enable (OE), and three-state drivers. Writing to the device is accom plished by taking chip enable one (CE-|) and write enable (WE) inputs LOW and chip enable two (CE 2 ) input HIGH. Data on

cy7c109l-15vi

Abstract: CY7C109L15VI CY7C109L CY7C1009 CY7C109 CY7C1009-15VI cy7c109-15zc CY7C109-15VI
Contextual Info: CY7C109 CY7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW max., 12 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low-power version) • 2.0V Data Retention (Low-power version) • Automatic power-down when deselected

ATPA

Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C

CY7C1009

Abstract: CY7C109
Contextual Info: fax id: 1047 CY7C109 CY7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW max., 12 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power version) • Automatic power-down when deselected

81c78

Abstract: 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference
Contextual Info: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35C 2148-35M 2148-45C 2148-45C 2148-45M 2148-45M+ 2148-55C 2148-55C 2148-55M 2149-35C 2149-35C 2149-35M 2149-45C 2149-45M 2149-45M 2149-55C 2149-55C 2149-55M

MSM 6290

Abstract: msm 5562 27c256 intel 62c512 AP 2068 27C512 microchip 62256 57C256 27C512 SGS-THOMSON 27C512-150
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 2147-35C 27S07AC 7C190-25C 7C171A-35C 7C171A-25C 2147-45C 7C147-45C 27S07AM 7C190-25M 7C171A-45M 7C171A-35M+ 2147-45M+

G 1009l

Abstract: CY7C1009 CY7C109
Contextual Info: fax id: 1047 CY7C109 CY7C1009 CYPRESS 128K x 8 Static RAM Features active HIG H chip enable C E 2 , an active LO W ou tput enable (OE), and three -state drivers. W riting to the device is a cco m ­ plished by takin g chip enable one (CE-|) and w rite enable (WE)

Contextual Info: C Y 7 C 1 0 0 9 C Y 7 C 1 0 9 CYPRESS 128K 8 Static RAM active HIGH chip enable CE2 , an active LOW output enable (OE), and three-state drivers. Writing to the device is accom­ plished by taking chip enable one (CE-|) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on

CY7C1009

Abstract: CY7C109 7C109-25 cypress cy7c109-20zi
Contextual Info: CY7C109 CY7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW max., 12 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power version) • Automatic power-down when deselected

CY7C109L

Abstract: CY7C109L-15VI 7C1009 A15C CY7C1009 CY7C109
Contextual Info: CY7C109 CY7C1009 CYPRESS 128K Features 8 Static RAM able OE , and th re e -sta te drivers. W ritin g to the device is ac­ com p lish ed by takin g C hip Enable O ne (CE-|) and W rite En­ able (W E) inputs LO W and C hip Enable Two (CEg) input HIGH. D ata on the eigh t I/O pins (l/O 0 throu gh l/ 0 7) is then w ritten

27HC642

Abstract: 39C10B PAL22V10APC CY2254SC-1 7132SA70 93L422AM 7024S15 7130SA25 7C198-45C 7006S
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 2147-35C 27S07AC 7C190-25C 7C171A-35C 7C171A-25C 2147-45C 7C147-45C 27S07AM 7C190-25M 7C171A-45M 7C171A-35M+ 2147-45M+

CY7C1009-15VC

Contextual Info: C Y 7 C 1 0 0 9 C Y 7 C 1 0 9 P Yi. PX :V «*1 128K 8 Static RAM active HIGH chip enable CE2 , an active LOW output enable (UE), and three-state drivers. Writing to the device is accom­ plished by taking chip enable one (CEi) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on

San Ace 40

Abstract: CY7C1009 CY7C109
Contextual Info: 1CY 7C10 9 CY7C1009 CY7C109 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 853 mW max., 15 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power version) • Automatic power-down when deselected

CY7C1009

Abstract: CY7C109
Contextual Info: 009 CY7C109 CY7C1009 128K x 8 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1017 mW max., 12 ns • Low CMOS standby power — 55 mW (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power version) • Automatic power-down when deselected

CY7C109

Abstract: CY7C109-15PC CY7C109-15VC CY7C109-20PC CY7C109-20VC 7C10925
Contextual Info: CY7C109 128K x 8 Static RAM Features Functional Description D The CY7C109 is a highĆperformance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable CE1 , an active HIGH chip enable (CE2), an active

5962L0053605VYC

Abstract: 5962-9069204QXA ATMEL 302 24C16 UT9Q512E-20YCC MOH0268D UT54ACS164245SEIUCCR Z085810 5962-9762101Q2A UT28F256QLET-45UCC 5962R0250401KXA
Contextual Info: NOT MEASUREMENT SENSITIVE MIL-HDBK-103AJ 19 SEPTEMBER 2011 SUPERSEDING MIL-HDBK-103AH 28 MARCH 2011 DEPARTMENT OF DEFENSE HANDBOOK LIST OF STANDARD MICROCIRCUIT DRAWINGS This handbook is for guidance only. Do not cite this document as a requirement. AMSC N/A

7C109-35

Abstract: 7C108
Contextual Info: K 'ß CY7C108 CY7C109 AD VAN CED IN F O R M A TIO N SEMICONDUCTOR 131,072 x 8 Static R/W RAM Features F unctional D escription • High speed T h e CY7C108 and CY7C109 are high-per­ form ance C M O S static R A M s organized as 131,072 words by 8 bits. Easy m em ory expansion is provided by an active L O W chip