777T7 Search Results

AM9517A

Abstract: AM53C80N AM5380 processor VIA C7-D
Contextual Info: Am5380/Am53C80N* SCSI Interface Controller DISTINCTIVE CHARACTERISTICS SCSI Interface • • • • • • CPU Interface Asynchronous interface to 1.5 megabytes per second Supports Initiator and Target roles Parity generation with optional checking Supports Arbitration

BI71

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are provided for

upd4265

Abstract: 4265 AAFW
Contextual Info: SEC /iP D 4 2 6 5 6 5 ,5 3 6 x 1 -B IT D Y N A M IC CMOS RAM NEC Electronics Inc. Revision 1 Pin Configuration D e scrip tio n T h e N E C /UPD4265 is a 6 5 ,5 3 6 -w o rd b y 1 -b it d y n a m ic C M O S R a n d o m A c c e s s M e m o ry R A M d e s ig n e d to

Contextual Info: MOSEL- VITELIC MS628128 1048576 131,072 x 8 CMOS STATIC RAM WITH DATA RETENTION AND LOW POWER ADVANCED INFORMA TION Features Description • Available in 80/100/120 ns (Max.) ■ Automatic power-down when chip disabled ■ Lower power consumption: MS628128

Contextual Info: M OSEL VITELIC V54C36516G4V 166/143 MHz 3.3 V 0L T 4M X 16 ULTRA HIGH PERFORMANCE SDRAM 4 BANKS X 1Mbit X 16 PRELIMINARY 6 7 S y s te m F re q u e n c y fCK 166 M H z 143 M H z C lo c k C y c le T im e (tcK 3 ) 6 ns 7 ns C lo c k A c c e s s T im e (tAC3) C A S L a te n c y = 3

Contextual Info: AUe Gewinde MB durch die e r s t e Rippe o LD O xl ON 29 10 LD rn 30 50 70 90 100 S c h u t z v e r m e r k n a c h D IN 3 4 F is c h e r E le k t r o n ik 1999 F r e im a s s t o le r a n z O b e r fla c h e D IN 2 7 6 8 m fikchtrclcktronik - E 3 #

R40 AH

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are

44 pin plcc package drawing

Abstract: 83B692 83C690 smc 83C690
Contextual Info: 83C694D INTRODUCTION 1.0 INTRODUCTION 1.1 DOCUMENT SCOPE This document describes the function and opera­ tion of the 83C694D Twisted-Pair Interface and Manchester Encoder/Decoder. It includes a de­ scription of external logic necessary for the efficient

KM641003J-15

Abstract: KM641003J-20
Contextual Info: CMOS SRAM KM641003 256K x 4 Bit With OE High-Speed CMOS Static RAM GENERAL DESCRIPTION FEATURES • Fast Access Time 15,17,20 ns(Max.) • Low Power Dissipation Standby (TTL) : 40 mA(max.) (CMOS): 10 mA(max.) Operating KM641003J-15 : 170 mA(max.) KM 641003J-17: 160 mA(max.)

777T7

Contextual Info: NEC MOS INTEGRATED CIRCUIT / ¿P D 4 2 1 6 4 0 5 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, HYPER PAGE MODE DESCRIPTION The /iPD4216405 is a 4 194 304 words by 4 bits dynamic CMOS RAM with optional hyper page mode. Hyper page mode is a kind of the page mode and is useful for the read operation.

HM5241

Abstract: HM5241605CTT15
Contextual Info: HM5241605C Series Preliminary 131,072-w ord x 16-bit x 2-bank Synchronous Dynam ic RAM H IT A C A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2 banks for improved performance. Features • 3.3 V Power supply

Contextual Info: EDI8L32512C ^ E D l S12Kx32 SRAM Module ELECTRONIC MSIGNS. NC. ADVANCED INFORMATION 512Kx32 CMOS High Speed Static RAM Features The EDI8L32512C is a high speed, high performance, four megabit density Static RAM organized as a 512Kx32 bit 512Kx32 bit CMOS Static

LA1160

Abstract: LA3370 LAII40 la1140 power ic of lg car stereo quadrature detector i8085
Contextual Info: Ordering number: EN 729E I SAfÊYO i M onolithic Linear IC No 729E FM IF S y s t e m fo r Car Us e The LA 1140 is an IF system IC designed for FM car stereo receivers. It features versatile muting characteristics and allows receiver designers to realize the

EDI8L32512C

Abstract: EDI8L32512C25AC
Contextual Info: EDI8L32512C ^ E D l S12Kx32 SRAM Module ELECTRONIC MSIGNS. NC. ADVANCED INFORMATION 512Kx32 CMOS High Speed Static RAM Features The EDI8L32512C is a high speed, high performance, four megabit density Static RAM organized as a 512Kx32 bit 512Kx32 bit CMOS Static

M 50556

Abstract: 50556 act mx hf nu
Contextual Info: [Ordering number : EN5055A ~| CMOS LSI No. 5055A SAXYO L C 3 8 2 1 6 1 T - 1 7 2 MEG 65536 words x 16 bits x 2 banks Synchronous DRAM Overview Package Dimensions The LC382I61T is a 3.3 V single-voltage power supply unit: mm synchronous D RAM s with a 65536-word x 16-bii x 2-

Contextual Info: PRELIMINARY July 1994 TP3420A ISDN S /T Interface Device General Description Features The TP3420A is an enhanced version o f the TP3420, with a number o f upgraded features for compliance with the new release o f ANSI T1.605-1991 and CCITT 1-430. A t initial

D42S18165

Contextual Info: DATA SHEET NEC / / MOS INTEGRATED CIRCUIT ¿ ¿ P D 42S 18165, 4218165 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE EDO , BYTE READ/WRITE MODE Description The /iPD42S18165,4218165 are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional hyper page mode

Contextual Info: Philips Semiconductors l2C Specific information The l2C-bus and how to use it The I C-bus and how to use it including specifications 1.0 THE l2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS H ere are s o m e of th e fe a tu re s o f th e l2C -bus: fro m th e bus.

4218160

Abstract: NEC 4218160 nec A2C UPD42S18160
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /JPD42S18160,4218160 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The /tPD42S18160, 4218160 are 1,048,576 words by 16 bits CMOS dynamic RAMs. The fast page mode and byte read/write mode capability realize high speed access and low power consumption.

NIPPON SMG

Abstract: 5216805 gt77
Contextual Info: HM5216405 Series Preliminary 2,097,152-word x 4-bit x 2-bank Synchronous Dynamic RAM HITACHI All Inputs and outputs are referred to the rising edge of the clock input. The HM5216405 is offered In 2 banks for improved performance. Features R b v . 0.1 Apr. 5 ,1 9 9 5

LC384161

Abstract: LC3841611-20 51165 A8AI I36S kiv 410 bsh17 FT28 SANYO 4F1 tda 1222
Contextual Info: ~ KNo. N5389 //VO . 6 3 8 9 43096 s .V CMOS LSI LC384161T-20 V '4 M !!3 :0 /2 7 -F x i6 t'7 h x 2 '< ^ ;-» ? Q « D R A K «fi t1"' LC384I61TIÌ, 1310729- 1<X 16fcf? h X 2/< > ÿ * j S m . 3 V * - * * I H i { l ! / / * '> V ÿ ö + * D R A N ^ f e Ä D R A M ? * * . WI5aCM OSlâI»tra«lÂlalïftiDffWJIci U, * & * , & & , {gfflU W Æ cO fSÂfcîtfc. .3 V

Contextual Info: ri fi ri v£D oo 21 S c h u t z v e r m e r k nach D IN 3 4 F is c h e r E le k t r o n ik 2 0 0 0 F re im a s s to le ra n z O b e r f la c h e D IN 2 7 6 8 m fi/cherelektronik H 3 € 3 # M a H s t a b = 2:1 D a tu m B e a r b . 0 4 .0 7 .0 0 Nam e

Contextual Info: vO OO 14 S c h u t z v e r m e r k nach D IN 3 4 F is c h e r E le k t r o n ik 2 0 0 0 F re im a s s to le ra n z O b e r f la c h e D IN 2 7 6 8 m € M a H s t a b = 3:1 3 fi/cherelektronik H 3 # D a tu m B e a r b . 0 4 .0 7 .0 0 Nam e H A R P A IN

Contextual Info: HM5241605C Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-381B Z Rev. 2.0 Jan. 7, 1997 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2 banks for improved performance.