74HC1 Search Results

IC 74HC112

Abstract: 74HC112
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141A Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2000

74HC109

Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features

CD74HC138MT

Abstract: CD74HC138M96E4 74HC138
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/

74HC

Abstract: 74HC126 74HC1G126 74HC1G126GV 74HC1G126GW 74HCT126 74HCT1G126 74HCT1G126GV 74HCT1G126GW
Contextual Info: 74HC1G126; 74HCT1G126 Bus buffer/line driver; 3-state Rev. 04 — 20 July 2007 Product data sheet 1. General description The 74HC1G126 and 74HCT1G126 are high-speed, Si-gate CMOS devices. They provide one non-inverting buffer/line driver with 3-state output. The 3-state output is

21A1

Abstract: 74LV125DB 74HC125 74HCT125 74LV125 74LV125D 74LV125N 74LV125PW JESD22-A114E
Contextual Info: 74LV125 Quad buffer/line driver; 3-state Rev. 03 — 7 April 2009 Product data sheet 1. General description The 74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC125 and 74HCT125. The 74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The

74HC123

Abstract: 74HCT123 74LV123 74LV123BQ 74LV123D 74LV123DB 74LV123N 74LV123PW SOT736-1
Contextual Info: 74LV123 Dual retriggerable monostable multivibrator with reset Rev. 05 — 8 November 2007 Product data sheet 1. General description The 74LV123 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC123; 74HCT123. It is a dual retriggerable monostable multivibrator which

CD54HC158

Abstract: CD74HC158 HC157 HC158
Contextual Info: [ /Title CD74H C157, CD74H CT157, CD74H C158, CD74H CT158 /Subject (High Speed The CD54HC158 and 74HC158 are obsolete and no longer are supplied. CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158 Data sheet acquired from Harris Semiconductor SCHS153B

Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/

74hc169

Abstract: 74HC MM74HC169
Contextual Info: MM54HC169/74HC169 PRELIMINARY n National zA Semiconductor microCMOS M M 54H C 169/M M 74H C 169 4-Bit Up/Down Synchronous Binary Counter General Description These cou nters are im plem ented using an advanced 3.0 m icron s ilic o n gate N-well m icroC M O S process to

SCHS142F

Abstract: 74HC123 74HC123 timing application circuits of ic 74HC123 CD54HC123F3A CD54HCT123F3A CD74HC123E CD74HC123M CD74HC123M96 CD74HC123MT
Contextual Info: [ /Title CD74 HC123 , CD74 HCT12 3, CD74 HC423 , CD74 HCT42 3 /Subject (High Speed CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Data sheet acquired from Harris Semiconductor SCHS142F September 1997 - Revised October 2003 High-Speed CMOS Logic Dual Retriggerable

HC192

Contextual Info: [ /Title CD74 HC192 , CD74 HC193 , CD74 HCT19 3 /Subject (High Speed CMOS Logic Preset- CD54/74HC192, CD54/74HC193, CD54/74HCT193 Data sheet acquired from Harris Semiconductor SCHS163D September 1997 - Revised December 2002 High Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

CD74HCT138/238

Contextual Info: Technical Data File N um b er CD54/74HC138, CD54/74HCT138 CD54/74HC238, CD54/74HCT238 1477 HARRIS SEMICOND SECTOR 57E D B 4302E71 DQlTSTh 0 « H A S High-Speed CMOS Logic H C /H C T H C /H C T 238 138 m -v o d f i i ; 12 Y3 - l i — Y4 - y - v s Y6 — — Y7

74HC123

Abstract: 74HC123D 74hc123 application note 74hc123 application notes 74HCT123D 74HCT123N 74HCT423 74HC123N 74HC423 74HCT123
Contextual Info: 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Rev. 6 — 14 March 2011 Product data sheet 1. General description The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL LSTTL . They are specified in compliance with JEDEC

Contextual Info: [ /Title CD74 HC139 , CD74 HCT13 9 /Subject (High Speed CMOS Logic Dual 2-to-4 Line Decod CD54/74HC139, CD54/74HCT139 Data sheet acquired from Harris Semiconductor SCHS148B High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer September 1997 - Revised May 2000

C6093

Abstract: 74HC138A HC138A ADI1455 HC138 LS138 MC54HCXXXAJ MC74HCXXXAD MC74HCXXXAN
Contextual Info: Order this data sheet by M C54/74HC138A/D MOTOROLA S E M IC O N D U C TO R TECHNICAL DATA MC54/74HC138A Advanced Information J SUFFIX CERAMIC CASE 620-09 1 -o f- 8 D e c o d e r /D e m u ltip le x e r H ig h -P erfo rm a n ce S ilic o n -G a te C M O S N SUFFIX

74HC181

Abstract: MC74HCXXXN ls181 74HC series j 182 74HC 74HC LOGIC PINOUT
Contextual Info: g M OTOROLA MC54/74HC181 Product P re v ie w HIGH-PERFORMANCE CMOS LOW -POWER CO M PLEM ENTARY MOS S ILICO N-G ATE 4-BIT ARITHMETIC LOGIC UNIT The M C54/74HC181 is identical in p in o u t to the L S I81. The device in­ puts are com p a tib le w ith standard CM OS o utputs; w ith pullup

CD74HCT107

Abstract: CD54HC107F3A CD54HCT107F3A CD74HC107E HC107 HCT10
Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/74HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002

Contextual Info: GD54/74HC165, GD54/74HCT165 8-BIT PARALLEL-IN/SERIAL-OUT SHIFT REGISTER General Description Pin Configuration These devices are identical in pinout to the 5 4 /74L S 16 5 . This circuit is an 8-bit, parallel-input to serial-output shift register with complementary

74hc161 application notes

Abstract: 74hc16 hc160 74HC163 54hc binary counters 74HC162 Thomson capacitors lcc M54HCXXXF1R IC 74LS160
Contextual Info: M54/74HC160/161 M54/74HC162/163 SYNCHRONOUS PRESETTABLE 4-BIT COUNTER . . . . . . . HIGH SPEED fMAX = 63 MHz TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS tPLH = tPHL

74HC164N PIN DIAGRAM

Abstract: 74hc164n 74HCT164 application note 74HC164 74HCT164 74HCT164BQ 74HC164D 74HC164DB 74HCT164D 74HCT164DB
Contextual Info: 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Rev. 5 — 25 November 2010 Product data sheet 1. General description The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL LSTTL . They are specified in compliance with JEDEC

74HC163

Abstract: CP/2014
Contextual Info: 74HC163; 74HCT163 Presettable synchronous 4-bit binary counter; synchronous reset Rev. 3 — 2 June 2014 Product data sheet 1. General description The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked

74HC163

Abstract: CP/2014
Contextual Info: 74HC163-Q100; 74HCT163-Q100 Presettable synchronous 4-bit binary counter; synchronous reset Rev. 1 — 19 June 2014 Product data sheet 1. General description The 74HC163-Q100; 74HCT163-Q100 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops

Contextual Info: 74HC175; 74HCT175 Quad D-type flip-flop with reset; positive-edge trigger Rev. 3 — 31 March 2014 Product data sheet 1. General description The 74HC175; 74HCT175 are high-speed Si-gate CMOS devices which are pin compatible with Low-power Schottky TTL LSTTL .

PC 74HC139

Contextual Info: [ /Title CD74 HC139 , CD74 HCT13 9 /Subject (High Speed CMOS Logic Dual 2-to-4 Line Decod CD54/74HC139, CD54/74HCT139 Data sheet acquired from Harris Semiconductor SCHS148B High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer September 1997 - Revised May 2000