74LS73A Search Results

Contextual Info: GD54/74LS73A DUAL NEGATIVE EDGE-TRIGGERED MASTER-SALVE J-K FLIP-FLOPS WITH CLEAR AND COMPLEMENTARY OUTPUTS Description Pin Configuration This device contains two independent negativeedge-triggered J-K flip-flops with complementary out­ puts. The J and K data is processed by the flip-flops

M74LS107AP

Abstract: 20-PIN M74LS73AP
Contextual Info: M IT S U B IS H I LSTTLs M 74LS 73A P DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH R ESET DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS73A P c o n ta in in g 2 J -K is a s em ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits

74LS73A

Contextual Info: M M O TO R O LA SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS/74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may

74LS73A

Abstract: 751A-02
Contextual Info: SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may

74LS73AP

Abstract: 12 V T flip flop IC JK flip flop IC M74LS73 M74LS107AP M74LS73AP 74LS73 20-PIN flip flop T Toggle T flip flop pin configuration
Contextual Info: M ITSUBISHI LST T Ls M 74LS 73A P DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH R ESET DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS73A P c o n ta in in g 2 J -K is a s em ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits

74LS73A

Abstract: truth table NOT gate 74 751A-02
Contextual Info: SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may

Contextual Info: Ä MOTOROLA SN54/74LS73A D E S C R IP T IO N - The S N 5 4 L S /7 4 L S 7 3 A offers individual J, K, clear, and clock inputs. T h e se dual flip-flops are designed so th at w h e n th e clock goes H IG H, th e inputs are enabled and data w ill be accepted. The

C350AVB

Abstract: full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder
Contextual Info: FUJITSU MICROELECTRONICS F U JIT S U wmmm 7flC D B 37MT7bH □D03c]4b 3 • JZ CMOS Gate Array GENERAL INFORMATION The Fujitsu CM O S gate array fam ily consists of tw en tyeight device types which are fabricated w ith advanced silicon gate CMOS technology. And more than 14 devices

J-K Flip flops

Abstract: LS73A LS73 SN5473 SN54LS73A SN74 SN7473 SN74LS73A
Contextual Info: SN5473, SN54LS73A, SN7473, 74LS73A □UAL J-K FLIP-FLOPS WITH CLEAR SDLS118 DECEMBER 1983 - • Package Options Include Plastic "Small Outline'' Packages. Flat Packages, and Plastic and Ceramic DIPs REVISED MARCH 1988 S N 5 4 7 3 . S N 5 4 L S 7 3 A . . . J OH W PA CK A G E

EATON CM20A

Abstract: A5 GNE mosfet Hall sensor 44e 402 2N8491 FTG 1087 S TRIAC BCR 10km FEB3T smd transistor marking 352a sharp EIA 577 sharp color tv schematic diagram MP-130 M mh-ce 10268
Contextual Info: Table of Contents N E W A R K E L E C T R O N IC S “Where serving you begins even before you call” Newark Electronics is a UNIQUE broadline distributor of electronic components, dedicated to provid­ ing complete service, fast delivery and in-depth inventory. Our main

74LS107A

Contextual Info: M MOTOROLA SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the

7054F

Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
Contextual Info: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
Contextual Info: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

74LS107A

Abstract: 74LS73A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS73
Contextual Info: SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the

74ls185

Abstract: ttl 74ls185 74LS165 Counter counts from 1-6 using 74ls161 8800-T v8810 74ls161 counter pin configuration IC 74LS185 pin diagram PMI DAC8800 AC-8800
Contextual Info: ANALOG ► DEVICES AN-142 APPLICATION NOTE ONE TECHNOLOGY WAY • P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700 Voltage Adjustment Applications of the DAC-8800 TrimDAC An Octal, 8-Bit D/A Converter <S> by J o * Buxton The DAC-8800, a monolithic octal 8-bit digital-to-analog converter,

LS73A

Abstract: SN5473 SN54LS73A SN7473 SN74H73 SN74LS73A
Contextual Info: TYPES SN5473, SN54H73, SN54L73, SN54LS73A, SN7473, SN74H73, 74LS73A DUAL J-K FLIP-FLOPS WITH CLEAR _ P ackage Options Include Plastic and C eram ic DIPs • R E V IS E D D E C E M B E R 1 9 8 3 S N 5 4 7 3 , S N 5 4 H 7 3 , S N 5 4 L S 7 3 A . . . J OR W P AC KA G E

74LS73AN

Abstract: Q356
Contextual Info: R C H U - P S E M IC O N D U C T O R tm 74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs sition tim e of th e negative going edge o f the clock pulse. The data on the J and K inputs is allowed to change w hile the

Contextual Info: TYPES SN5473, SN54H73, SN54L73, SN54LS73A, SN7473, SN74H73, 74LS73A DUAL J- K FLIP-FLO PS WITH CLEAR E V IS E D D E C E M B E R 1 9 8 3 • * Package Options Include Plastic and ■ Ceramic DIPs

74LS82

Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
Contextual Info: GOULD 4055916 GOULD SEMICONDUCTOR SEMICONDUCTOR DIV DIV 03E D | 03E MDSSTlb 09920 D UCICmEU T-4 3I-V 7400 TTL Cells •> GOULD CM OS Gate Array and Standard Cell Library Electronics Features General Description • Over 200 functions available. 7400 TTL Cells, a member of Gould’s EXPERT ASIC

LS73A

Abstract: SN5473 SN54LS73A SN74 SN7473 SN74LS73A SNS473
Contextual Info: SN5473, SN54LS73A, SN7473, 74LS73A DUAL J K FLIP-FLOPS WITH CLEAR DECEMBER 1983 - • Package Options Include Plastic "Small Outline" Packages, Flat Packages, and Plastic and Ceramic DIPs • Dependable Texas Instruments Quality and Reliability REVISED MARCH 1988

lvc16244

Abstract: BC240 2sk3174 CBT1G125 LV2GT14A HC32 Hitachi HA13557A transistor 2SC1162 H8 hitachi programming manual 30204SP
Contextual Info: HITACHI ELECTRONIC COMPONENTS DATABOOK 2003 INDEX General Informations Multi Perpose Products Safety Considerations Hitachi Semiconductor Package Databook HITACHI Sales Locations Diodes Microcontroller Microcontroller General Microcontroller Overview List

1S2074

Abstract: HD74LS73A IS2074
Contextual Info: • Dual J-K Flip-Flops with Clear • PIN A R R A N G E M E N T ■ B L O C K D IA G R A M ( ^ ) ■ R E C O M M E N D E D O PER A TIN G C O N D IT IO N ■ F U N C T IO N TABLE In p u ts C le a r C lock J K L X X L H Item O u tp u ts Q j X L 1 L Qi* Sym bol