74LS27 Search Results

8253/8254

Abstract: md 8243 ITT301 6168 sc 8254 AA lt 8239 signetics B197 B236 B237
Contextual Info: Signetics Integrated C ircuits-Lo w Power Schottky T T L TYPE NO. d e s c r ip t io n STO C K NO. N74LS 260N N 74LS261N IN74LS266N Dual 5 -In p u t NO R Gate M u ltip ly Decoder Quad Exclusive NOR 5S 735A 55 7 3 6 X 5 57 37H O U T L IN E DRW G. NO. 1 2 1 M 74LS273N

CI 7446

Abstract: CI 74141 cI 74ls47 CI 7447 CI 7448 ci 7445 7-seg ANODE COMMON CI 74LS48 TTL 7446 BCD D147
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T TL 7 1 2 6 3 5 i Ao A RBO a A 2 b A3 e d 1 El e 13 12 11 10 RBI f 9 E 9 15 3 2 4 m l 14 6 m Do MR TTTTTTTT 4 D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 So Qo 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

7475 D flip-flop

Abstract: quad D flip-flop 74175 pin 4 bit shift register 7494 pin diagram latch 74ls574 7477 D latch 74174 shift register 9374 74LS173 4 bit 3 state quad register 74LS279 D flip-flop 74175 pin
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T TL 7 1 2 6 3 5 i Ao A R BO a A 2 b A 3 e d 1 E l RBI e 13 12 11 10 E 9 f 9 15 3 2 4 m l 14 6 m Do M R TTTTTTTT 4 D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 So Qo 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

74LS273

Abstract: pin diagram of 74ls273 1619CP SN54LSXXXJ SN74LSXXXN
Contextual Info: SN54/74LS273 OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3

74LS273

Abstract: DTLLA 74S273 74LS N74LS273D N74LS273N N74S273D N74S273N 74LS273 equivalent FM04
Contextual Info: Signetics 74LS273, S273 Flip-Flops Octal D Flip-Flops Product Specification Logic Products FEATURES • Ideal buffer for MOS microprocessor or memory • Eight edge-triggered D flip-flops • High speed Schottky version available • Buffered common clock

Contextual Info: M O TO ROLA SN54/74LS27 =Ì£> T R IP LE 3-tNPUT NOR GATE u l d Ld Ld LdiJ Ld LsJ LId z LO W POW ER SCHO TTKY J Suffix — Case 632-08 Ceramic N Suffix — Case 646-06 (Plastic) GUARAN TEED OPERATING RANGES SYM BO L MIN TYP MAX UNIT vcc Supply Voltage PARAM ETER

7427 SIGNETICS

Abstract: 7427 pin configuration LS-27 74LS27 pin configuration
Contextual Info: 7427, LS27 Signetics Gates Triple Three-Input NOR Gate Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 7427 9ns 13mA 74LS27 10ns 2.7mA ORDERING CODE COMMERCIAL RANGE VCC = 5 V ± 5 % ; T a = 0°C to + 7 0 ”C

74LS273

Contextual Info: Am25LS273 • Am25LS273B Am54LS/74LS273 8-Bit Register with Clear 8-Bit Register with Clear and Buffered Outputs DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • Eight-bit, high-speed parallel registers • Clock to output delay - 15ns typ on Am25LS273

Contextual Info: I LS TTL DN74LS Series 74LS27 74LS27 Triple 3 - input Positive NOR Gates P-1 • Description DN 74LS27 contains three 3-input positive isolation NOR gate circuits. ■ Features • • • • Low pow er consum ption Pd = 13.5mW typical High speed ( t pd = 10ns typical)

SN74LS27

Abstract: SN7427 kd 617 TTL SN7427 LS27 SN5427 SN54LS27 SN74
Contextual Info: | SN5427, SN 54LS27, SN7427, SN 74LS27 TRIPLE 3 INPUT POSITIVENOR GATES SDLS089 DECEMBER 1 9 8 3 -R E V IS E D M A H C H 1 3 8 8 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

74198

Abstract: 74LS194 74198 pin diagram 54LS D172 D173 74LS273 74LS323 74ls273 fairchild 74LS398
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL 088 54LS/74LS299 11 18 Vcc Pin 20 QND = Pin 10 D89 54LS/74LS323 Vcc = Pin 20 QND = Pin 10 D90 54LS/74LS273 3 4 7 8 13 14 17 18 Vcc = Pin 20 GND = Pin 10 D91 54LS/74LS377 1 3 4 7 8 13 14 17 18 Vcc = Pin 20 GND = Pin 10

ci 7475

Abstract: 74175 pin 9374 D147 93L38 74LS75 7477 D latch 74LS77 9370 DA 9370
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L 7 1 2 6 3 5 i Ao A R BO a A 2 b A 3 e d 1 E l RBI e 13 12 11 10 E 9 f 9 15 3 2 4 m l 14 6 m Do So M R TTTTTTTT 4 D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

IC 7402

Abstract: IC 7427 LS 7402 IC 7425 74LS27
Contextual Info: 7427 ycç IC 1Y 3C 38 3A 3Y ninirtiLrtin±niMir 1A OY=A+B+C IB 2A 28 2C 2Y GND - 39 - Triple 3 Input N OR Vcc 74LS27 m * 'J ' mu OUT N LS ALS tpd nax Kh L-»H t 15 15 15 6 .5 5 .5 23 26 ns tpd max H—*L I 11 15 9 5 4 .5 23 26 ns IN ALSK F S AS AC ACT K HCU

751B03

Abstract: 74ls279 of 74ls279 truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS279 QUAD SET-RESET LATCH VCC S1 R Q S1 S2 R Q 16 15 14 13 12 11 10 9 QUAD SET-RESET LATCH LOW POWER SCHOTTKY 1 2 3 4 5 6 7 8 R S1 S2 Q R S1 Q GND J SUFFIX CERAMIC CASE 620-09 16 TRUTH TABLE INPUT 1 S1 S2 R OUTPUT Q L L X H H L X L H H L H H L H

74ls characteristics

Abstract: 74LS279 S5427 74279 truth table NOT gate 74 N74279F N74279N N74LS279F N74LS279N S54279F
Contextual Info: PIN CONFIGURATION 54/74279 54LS/74LS279 ORDERING CODE PIN CONF. PACKAGES See Section 9 for further Package and Ordering Information. C O M M ER C IA L RANGES = + 5%; T a = 0 -C to *70"C VCC Plastic DIP Fig. A N74279N • 74LS279N C eram ic DIP Fig. A N74279F

74ls279

Abstract: diode s1 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 3S24 S211R
Contextual Info: SN54/74LS279 QUAD SET-RESET LATCH VCC 16 S1 15 R Q 14 13 S1 12 S2 11 R 10 Q 9 QUAD SET-RESET LATCH LOW POWER SCHOTTKY 1 R 2 S1 3 S2 4 Q 5 R 6 S1 7 Q 8 GND J SUFFIX CERAMIC CASE 620-09 16 TRUTH TABLE INPUT 1 S1 S2 R OUTPUT Q L L X H H L X L H H L H H L H

74S273

Abstract: 74LS273 SN74S273 IC 4017 B SN54/74S377
Contextual Info: 8-Bit Registers with Master Reset or Clock Enable SN 54/74LS273 S N 5 4 /7 4 S 2 7 3 S N 5 4 /7 4 LS 3 7 7 S N 5 4 /7 4 S 3 7 7 Features/Benefits Ordering Information • 20-Pin SKINNYDIP saves space PART NUMBER • 8-bit data path matches byte boundaries

74LS279

Contextual Info: 8 < > MOTOROLA SN54/74LS279 QUAD SET-RESET LATCH V cc s, R Q S2 S, R Q QUAD SET-RESET LATCH LOW POWER SCHOTTKY R S2 Si Q R Si Q f0n GND TRUTH TABLE INPUT J SUFFIX CERAMIC CASE 620-09 1 OUTPUT Si S2 R <Q L L X H H L X L H H L H H L H h H H L No Change N SUFFIX

IC 74LS273

Abstract: 74ls273 IC 74LS273 P pin diagram of 74ls273
Contextual Info: 74LS273, S273 Signetìcs Flip-Flops Octal D Flip-Flops Product Specification Logic Products FEATURES • Ideal buffer for MOS microprocessor or memory • Eight edge-triggered D flip-flops • High speed Schottky version available • Buffered common clock

74LS273

Contextual Info: NATIONAL SEUICOND i L O G I O 31E D • T-46-Û7-11 bSD112a 0071^53 3 ■ K74CF273 OCTAL D-TYPÊ FLIP-FLOPS WITH CLEAR PRELIMINARY 2/12/88 Functional Description The K74CF273 incorporates ferroelectric memory cells with the 74LS273 to produce a logic device functionally compatible with the 74LS273 that retains the output state of the device

Contextual Info: LS TTL DN74LS Series 74LS279 74LS279 10741^7*7 Quad S -K Latches • Description P -2 D N 74LS279 contains fo u r R-S flip-flop circuits. ■ Features • • • Low pow er consum ption Pa = 19mW typical Low o u tp u t im pedance Wide operating tem perature range (T a = - 2 0 to +75°C )

7475 d-flip flop

Abstract: 7475 D flip-flop ci 7475 D134 1CN 24 12 74175 74279 9374 FLIP FLOP 7475 Register 7475
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T TL 7 1 2 6 3 5 1 A R BO a A 2 b A 3 e d E l RBI e E 9 f 13 12 11 10 9 15 2 4 14 6 m Do M R TTTTTTTT 4 3 m i l Ao D147 54/74279, 54LS/74LS279 0146 9314, 93L14 D145 9370, 9374 So Qo 7 11 Da $3 V cc iwiEiEi[i3ii«inF5if»i

Contextual Info: SANYO SEMICONDUCTOR CORP 1SE » I 7 m u 7 b □□0Sk3'i C M O S H ig h -S p eed Standard Log ic L C 7 4 H C Series 3034A Triple 3-Input N O R Gate E2185 Features • The L C 7 4 H C 2 7 M consists of 3 identical 3-input N O R gates. • Uses C M O S silicon gate process technology to achieve operating speeds sim ilar to L S -T T L (74LS27 w ith the

Contextual Info: GD54/74LS273 OCTAL D-TYPE FLIP-FLOPS COMMON CLOCK SINGLE-RAIL OUTPUTS Feature • • • • Pin Configuration Contains Eight Flip-Flops with Single-Rail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: