74LS15 Search Results

IC 74LS153

Abstract: 74153 mux cd 74153 ic 74153 IC - 74LS153 74LS153 8 to 1 mux 74LS153 74153 74s153 2C011
Contextual Info: SN54153, SN 54LS153, SN 54S1S3 S N 74153, SN 74LS153, SN 74S153 DUAL 4 LINE TO 1-LINE DATA SELECTORSfM ULTIPLEXERS D E C E M B ER 1972 - R E V IS E D M A R C H 19B8 Permits Multiplexing from N lines to 1 line S N 54153, SN 5 4 LS1 5 3 , SN 5 4 S1 5 3 . . . J OR W

Diode RL 4B

Abstract: DN74LS158 MA161
Contextual Info: LS TTL DN74LS Series 74LS158 74LS158 Quad 2 -lin e to 1 -lin e Data S electors / Multiplexers • Description P -2 D N 74LS158 contains four 2-line to 1-line data selector/ m ultiplexer circuits. ■ Features • • • • • Inverted o u tp u t C om m on enable in p u t for all fo u r circuits

LS251

Abstract: 74LS151 multiplexers 74 LS 150 LS 74LS151 pin diagram 41 multiplexer 74ls151 74 LS 151 Logic DIAGRAM eight input multiplexer 54LS251 74LS1 74LS251
Contextual Info: Am25LS151 • Am54LS/74LS151 Am25LS251 • Am54LS/74LS251 Eight-Input Multiplexers L O G IC D IA G R A M D IS T IN C T IV E C H A R A C T E R IS T IC S • • • • S w itches o n e -o f-e ig h t in p u ts to tw o co m p le m e n ta ry o u tp u ts S ta n d ard , 'L S 15 1 and three-state, 'L S 25 1 o u tp u t versions

motorola zc 5276

Abstract: 74LS158 circuit diagram of 32-1 multiplexer LS158 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS158 QUAD 2-INPUT MULTIPLEXER The LSTTL/ MSI SN54L/ 74LS158 is a high speed Quad 2-input Multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the selected data in the

FAST AND LS TTL

Abstract: 751A-02 b8pl
Contextual Info: SN54/74LS15 TRIPLE 3-INPUT AND GATE TRIPLE 3-INPUT AND GATE VCC 14 LOW POWER SCHOTTKY 13 12 11 10 9 * 8 * * 1 2 3 4 5 6 J SUFFIX CERAMIC CASE 632-08 7 14 GND * OPEN 1 COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

74LS15

Abstract: 751A-02
Contextual Info: SN54/74LS15 TRIPLE 3-INPUT AND GATE TRIPLE 3-INPUT AND GATE VCC 14 LOW POWER SCHOTTKY 13 12 11 10 9 * 8 * * 1 2 3 4 5 6 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 * OPEN COLLECTOR OUTPUTS N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

Contextual Info: GD54/74LS157 QUADRUPLE 2-T0-1-LINE DATA SELECTORS/MULTIPLEXERS NON INVERTED DATA OUTPUTS Feature • • Buffered Inputs and Outputs Common Strobe/Select input for all 4 circuits. Pin Configuration INPUTS Vcc S TRO BE 4 A 4B G 4B INPUTS O U TP U T -. O UTPUT

74191 8 bit

Abstract: 7443 Flip-Flop D134 7443 d Flip-Flop 74LS42 74155 9B23 D135 93L38 93L11
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

74LS190 PIN diagram

Abstract: ttl 7442 74LS42 74LS138 pin diagram D134 7442 pin diagram 74155 74145 D133 93L01
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

7448 decoder

Abstract: ID 9302 Fairchild 74190 pin diagram decoder 7447 TTL 7448 74LS47 74LS47 pin TTL 7446 decoder 74LS47 decoder 7448
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 G N D = Pin 8 Vcc = Pin 16 G N D = Pin 8

transistor d133

Abstract: Decoder BCD 7 seg ttl 7442 transistor 6B 7-seg ANODE COMMON 74155 74LS247 pin diagram of 74LS247 ttl 74191 75491
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

ALU IC 74181

Abstract: 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 7411 3 INPUT AND gate TTL 74ls83 pin diagram of 7411 logic diagram of 7432
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 Vcc Vcc 1^1FH [iä| [vii Eòi [T| r»1 füi Fai np f i ! Föi lyi rn

74LS156FC

Abstract: 54156DM 54LS156DM 74156DC 74156FC 74156PC 74LS156PC 74ls156
Contextual Info: 15b T -6 6 -2 1 -5 3 _ C O N N E C T IO N D IA G R A M P IN O U T A 54/74156 54LS/74LS156 D U A L 1 - 0 F - 4 D E C O D E R / D E M U L T IP L E X E R With Open-Collector Outputs OUT A » [3 «3*0 6 *1 « Ô J/ V ) 23 Ö* 0.[é ïï] ô f c ou g go»

multiplexers 74LS 150

Abstract: 54LS 74LS
Contextual Info: GD54/74LS153 DUAL 4-LINE TO 1 - LINE DATA SELECTORS/MULTIPLEXERS Feature Pin Configuration • Permits Multiplexing from N Lines to 1 Line • Performs Parallel-to-Serial Conversion • Strobe Enable Line Provided for Cascading (N Lines to n Lines) • High-Fan-Out, Low-lmpedance, Totem Pole

74LS153

Abstract: 74LS153 multiplexer truth table TTL 74ls153 74ls153 application notes MSI 74LS153 multiplexor 74LS153 LS153 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS153 DUAL 4-INPUT MULTIPLEXER The LSTTL / MSI SN54 / 74LS153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select two bits of data from four sources. The two buffered outputs present data in the true non-inverted form. In addition to multiplexer

TTL 74ls153

Abstract: 74LS153 multiplexer truth table
Contextual Info: MOTOROLA SN54/74LS153 DUAL 4-INPUT MULTIPLEXER The LSTTL/M SI SN 54/74LS 153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select two bits of data from four sources. The two buffered

74LS155

Contextual Info: MOTOROLA SN54LS/74LS155 SN54LS/74LS156 D E S C R IP T IO N — T h e S N 5 4 L S /7 4 L S 1 55 and S N 5 4 L S /7 4 L S 1 56 are high speed Dual 1-of-4 D ecoder/D em ultiplexers. These devices have tw o decoders w ith comm on 2-bit Address inputs and separate gated

74S153

Abstract: 74LS153
Contextual Info: GD54/74LS153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS Feature Pin Configuration • Permits Multiplexing from N lines to 1 line • Performs Parallel-to-Serial Conversion • Strobe Enable Line Provided for Cascading (N Lines to n Lines) • High-Fan-Out, Low-lmpedance, Totem-Pole

74151APC

Abstract: of ic 74ls151 pin d 74151ADC 74LS151PC 74ls151 54151A TPL-34/12X46F
Contextual Info: N AT IONAL SEMICOND -CLOGIO DEE D 1 0 1 I bSDiiBE OGbaaafi 4 I C O N N E C T IO N D IA G R A M PIN O U T A T-66-21-53 54/74151A 54S/74S151 54LS/74LS151 13[T 8 -IN P U T M U L T IP L E X E R Vcc I2 U D m Il [ I 7 3 Is io [ T 13] 16 z[s m I? zK 1 Î] So iE TÖ] S i

Contextual Info: SA NY O SEMICONDUCTOR CORP 12E D I ^ L C 7 4 H G 1 5 4 - i-l’7 z i - $ S CM OS High-Speed Standard Logic LC74H C Series 3084 - 4 : 7 eH7Q7Li DGDShiS fl í ~ to 1 6 - L in e D e co d e r C1740A Features ~ • The LC74HC154 is a 4-to-16 decoder. • Uses CMOS silicon gate process technology to. achieve operating speeds similar to L S 'T T L 74LS154 gates with the

Contextual Info: GD54/74LS157 QUADRUPLE 2-T0-1-LINE DATA SELECTORS/MULTIPLEXERS NON INVERTED DATA OUTPUTS Feature Pin Configuration • • Buffered Inputs and Outputs Common Strobe/Select input for all 4 circuits. INPUTS Vcc STROBE 4A Descriptions j _ 16 j _ j j 5 j _ This monolitic data selector/multiplexer contains

DN74LS153

Abstract: MA161
Contextual Info: I 74LS153 LS TTL DN74LS Series 74LS153 Dual 4-lin e to 1-line Data Selectors / Multiplexers • Description D N 74LS153 contains two 4-line to 1-line data selector/ m ultiplexer circuits. P-2 ■ Features • Independent enable input for each circuit • Common selection input for both circuits

M74LS158P

Abstract: ic 4001 pin configuration diagram 20-PIN
Contextual Info: MITSUBISHI LSTTLs M 74LS158P QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER INVERTED DESCRIPTION The 74LS158P is a semiconductor integrated circuit containing four 2-line to 1-line data selector/multiplexer circuits. SELECTION INPUT FEATURES • •

DN74LS15

Contextual Info: I 74LS15 LS TTL DN74LS Series 74LS15 T rip le 3-input P o sitiv e AND G ates w ith Open C ollector Outputs P-1 • Description DN 74LS15 contains three 3-input positive isolation AND gate circuits w ith open collector o utputs. ■ Features • • •