74LS1 Search Results

74LS166A

Abstract: 54ls166a 54LS166
Contextual Info: SN54166, SN 54LS166A, SN74166. SN 74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS OCTOBER 1976 - REVISED MARCH 1988 S N 54166, S N 54LS 166A . . . J OR W PACKAGE S N 7416 6 . . . N PACKAGE S N 74LS 166A . . . D OR N PACKAGE • Synchronous Load • Direct Overriding Clear

IC 74LS153

Abstract: 74153 mux cd 74153 ic 74153 IC - 74LS153 74LS153 8 to 1 mux 74LS153 74153 74s153 2C011
Contextual Info: SN54153, SN 54LS153, SN 54S1S3 S N 74153, SN 74LS153, SN 74S153 DUAL 4 LINE TO 1-LINE DATA SELECTORSfM ULTIPLEXERS D E C E M B ER 1972 - R E V IS E D M A R C H 19B8 Permits Multiplexing from N lines to 1 line S N 54153, SN 5 4 LS1 5 3 , SN 5 4 S1 5 3 . . . J OR W

N74s174

Contextual Info: S N 5 4 1 74 , S N 5 4 1 75 , S N 5 4 L S 17 4 , S N 5 4 L S 17 5 , S N 5 4 S 1 7 4 , S N 5 4 S 175 , SN 74 174 , SN 74 175 , SN 74 LS 174, SN 74LS175, S N 74 S 174, SN74S175 HEX/QUADRUPLE D-TYPE FLIP FLOPS WITH CLEAR D E C E M B E R 1 9 7 2 - R E V l S E D M A R C H 1 9 8 8

ls125a

Abstract: ls126A 74LS126A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS125A SN54/74LS126A QUAD 3-STATE BUFFERS VCC E D O E D O 14 13 12 11 10 9 8 QUAD 3-STATE BUFFERS LOW POWER SCHOTTKY 1 2 3 E D O 4 5 6 7 E D O GND LS125A J SUFFIX CERAMIC CASE 632-08 VCC E D O E D O 14 13 12 11 10 9 8 14 1 N SUFFIX PLASTIC CASE 646-06

74LS169A

Abstract: 74LS168A 74S168A S168A 74S169
Contextual Info: 74LS168A, 74LS169A, S168A, S169A Signetics 4-Bit Bidirectional Counters 4-Bit Up/Down Synchronous Counter Product Specification Logic Products FEATURES • Synchronous counting and loading • Up/down counting • Modulo 16 binary counter — '169A • BCD decade counter — ' 168A

ttl 74ls10

Abstract: truth table NOT gate 74 74LS10 74LS10 truth table 751A-02 SN54-74LS10 74LS10 TTL 3 input nand gate 74LS10
Contextual Info: SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

74126PC

Abstract: 74126DC 74LS126PC 74LS126DC 74LS126 54126DM 54126FM 54LS126DM 54LS126FM 74126FC
Contextual Info: 126 CO NN ECTIO N DIAGRAM PINOUT A Ol 54/74126 0 i 0 54LS/74LS126 QUAD BUS BUFFER GATE With 3-State Outputs ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C Vcc = +5.0 V ±10%, T a = -55° C to +125°C

SO-140

Abstract: DN74LS12
Contextual Info: 74LS1 2 LS TTL DN74LS Series 74LS12 T rip le 3 - input P o sitiv e NAND G ates with Open C ollector Outputs • Description P-1 DN 74LS12 contains three 3-input positive isolation NAND gate circuits w ith open collector outputs. ■ Features • •

DN74LS125A

Abstract: MA161
Contextual Info: I LS TTL DN74LS Series 74LS125A 74LS125A Quad Bus Buffer Gates with 3 -sta te Outputs • Description P-1 DN 74LS125A contains four 3-state o u tp u t b uffer gate circuits, each w ith independent o u tp u t-co n tro l input-C term inals. ■ Features

DN74LS145

Contextual Info: LS TTL DN74LS Series 74LS145 74LS145 iv ^ L S ^ BCD to Decimal Decoders / Drivers P-2 • Description DN 74LS145 is a BCD to decim al decoder/ driver w ith open collector o u tp u ts. ■ Features • • • • Large o u tp u t cu rrent I o l ^ 80m A m axim um )

DN74LS194A

Abstract: MA161
Contextual Info: ! LS TTL DN74LS Series 74LS194A 74LS194A 4 -b it Bidirectional Universal Shift R egisters • Description P-2 DN 74LS194A is a bidirectional 4-bit serial/parallel input to serial/parallel output shift register. ■ • • • • • • Features Synchronous serial/parallel input to serial/parallel output

M74LS174P

Abstract: 20-PIN 251C
Contextual Info: MITSUBISHI LSTTLs M 74LS174P LOPS W IT H RESET HEX D -l DESCRIPTION The M 7 4L S 17 4P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing 6 D -type edge-triggered flip -flo p circuits w ith common clock input T and direct reset input R D as well

74174PC

Abstract: 74LS174PC 74LS174P 74174DC 74174FC 74LS174DC 74LS174FC 74S174DC 74S174FC 74S174PC
Contextual Info: 174 CONNECTIO N DIAGRAM PINOUT A 4/74174 54S /74S174 q 54LS/74LS174 \J a i / c c r-\ » mr[T 16] Vcc ïïla s Qo T HEX D FLIP-FLO P |T if] Ds t>i | T Î3ID4 d o Qi [7 12] Ds [6 T flP 3 Q îfT 101 0 3 g n d Q4 ~n cp [T DESCRIPTION — T h e ’17 4 is a high sp eed hex D flip -flo p . T h e d e vice is

DN74LS10

Abstract: MA161
Contextual Info: I LS TTL DN74LS Series 74LS10 74LS10 T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption P,j = 6mW typical High speed ( tpd = 10ns typical)

74160PC

Abstract: 74LS160 parallel counter 74LS160PC BCD Decade logic diagram 74160 74LS160D 74LS162 74LS160DC 74160 74LS162 parallel counter logic diagram of 74ls160
Contextual Info: 160 162 • CO NN ECTIO N DIAGRAM / n i * 54/74160 54LS/74LS160 S4LS/74LS162 ^ ^ 4 /7 4 1 6 2 P IN O U T A \ / ô / o ô ï o / ^S Y N C H R O N O U S PRESETTABLE BCD DECADE COUNTERS DESC R IP TIO N — The ’160 and '162 are high speed synchronous decade

74LS14PC

Abstract: 7414PC PIN OUT 74LS14 pin diagram of 7414 74LS14 5414DM schmitt trigger 7414 74LS14DC 7414DC 7414
Contextual Info: 14 CON NECTIO N DIAG RAM PINO UT A 54/7414 r '''54LS/74LS14 ¿v/ ' 7/ HEX SC HM ITT TRIGGER INVERTER I ORDERING CODE: See Section 9 PIN PKGS OUT Plastic DIP P A Ceramic DIP (D) A COMMERCIAL GRADE V cc = +5.0 V ±5%, T a = 0 °C to +70° C MILITARY GRADE

alu 74ls181

Abstract: 74LS181 Alu 181
Contextual Info: Am25LS181 • Am54LS/74LS181 Four-Bit Arithmetic Logic Unit/Function Generator L O G IC D I A G R A M D I S T IN C T I V E C H A R A C T E R IS T IC S • • • • P erform s 16 a rith m e tic o pe ra tio ns in c lu d in g add, su b tra ct, d o u b le and com pare

ATML U 010

Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H 74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

Contextual Info: Am25LS194A • Am54LS/74LS194A Am25LS195A • Am54LS/74LS195A Four-Bit High-Speed Shift Registers D IS TIN C TIV E C H AR A C TE R IS TIC S • • • • • LOGIC D IA G R A M S S hift righ t or parallel load w ith JK inputs on A m 25LS 195A S hift le ft, right, parallel load or do nothing on A m 25LS 194A

Diode RL 4B

Abstract: DN74LS158 MA161
Contextual Info: LS TTL DN74LS Series 74LS158 74LS158 Quad 2 -lin e to 1 -lin e Data S electors / Multiplexers • Description P -2 D N 74LS158 contains four 2-line to 1-line data selector/ m ultiplexer circuits. ■ Features • • • • • Inverted o u tp u t C om m on enable in p u t for all fo u r circuits

QE Logica 21

Abstract: 74ls164 74LS164 PIN DIAGRAM ad 440J AM25LS164DM 74ls gate symbols SN74LS164 74LS AM25LS164DC LS164
Contextual Info: Am25LS164 • Am54LS/74LS164 8-Bit Serial-ln, Parallel-Out Shift Register D IS T IN C T IV E C H A R A C T E R IS T IC S F U N C T I O N A L D E S C R IP T I O N • • T h e A m 2 5 L S 1 6 4 and A m 5 4 L S / 7 4 L S 1 64 are e ight-b it, serial in/parallel o u t sh ift registers bu ilt using advanced Low -Po w er

74LS190 up down decade counter

Abstract: 74LS190 PIN diagram 74LS190 pins 74LS190 ad 440J 74LS190 APPLICATIONS function 74ls190 74LS190 application
Contextual Info: Am25LS190 • Am54LS/74LS190 Am25LS191 • Am54LS/74LS191 Synchronous Counters With Up/Down Mode Control LO G IC D IA G R A M S D IS T IN C T IV E C H A R A C T E R IS T IC S • • • Single u p /d o w n c o u n tlin e Parallel load in p u ts and parallel c o u n t o u tp u ts

LS168A

Abstract: LS-168a LS168 sn74ls169an LS169A 74LS168 application note 25ls 74ls 74LS169A
Contextual Info: Am25LS168A • Am25LS169A Am54LS/74LS168A • Am54LS/74LS169A Synchronous Four-Bit Programmable Up-Down Counter F U N C T IO N A L D E S C R IP T IO N D IS T IN C T IV E C H A R A C T E R IS T IC S • • • • • A ll o p e ra tio n s are syn ch ro n o u s

LS251

Abstract: 74LS151 multiplexers 74 LS 150 LS 74LS151 pin diagram 41 multiplexer 74ls151 74 LS 151 Logic DIAGRAM eight input multiplexer 54LS251 74LS1 74LS251
Contextual Info: Am25LS151 • Am54LS/74LS151 Am25LS251 • Am54LS/74LS251 Eight-Input Multiplexers L O G IC D IA G R A M D IS T IN C T IV E C H A R A C T E R IS T IC S • • • • S w itches o n e -o f-e ig h t in p u ts to tw o co m p le m e n ta ry o u tp u ts S ta n d ard , 'L S 15 1 and three-state, 'L S 25 1 o u tp u t versions