LS155 Search Results

LS155

Abstract: 2CY19
Contextual Info: Dual 2-Line-To-4-Line Decoder/Demultiplexer With Three-State Outputs _ LS255 PIN-OUT DIAGRAM FEATURES • Three-state version of LS155 ■ A pplications: Dual 2-Lin e-to -4-L in e Decoder OUTPUT CONTROL I SELECT DATA I INPUT- nijTPUTS ° UT TS Dual 1 -U n e -to -4 -L in e D em u ltip lexer

LS155

Abstract: ALS155
Contextual Info: AVG Semiconductors_ DDi Technical Data Dual 1 of 4 Decoder/ Demultiplexer The LS155 is a high speed Dual one-of-four decoder/demul­ tiplexer. This device has two decoders with common two-bit Address inputs and separate gated Enable inputs. Decoder

dm74ls155n

Abstract: 54LS155DMQB 54LS155FMQB 54LS155LMQB DM54LS155J DM54LS155W LS155 LS156
Contextual Info: LS155*LS156 National Semiconductor LS155/LS155/LS155, 54LS156/DM54LS156/DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers General Description Features These TTL circuits feature dual 1-line-to-4-line demultiplex­ ers with individual strobes and common binary-address in­

74155 demultiplexer

Abstract: 74155 demultiplexer pin diagram and function table 74155 pin configuration 74155 demultiplexer pin configuration applications of 74155 74155 PIN DIAGRAM LS155 74 ls 155 demultiplexer 74LS155 dual 24 decoder 74155 signetics
Contextual Info: 7 4 1 5 5 , LS155 Signetics Decoders/Demultiplexers Dual 2-Line To 4-Line Decoder/Demultiplexer Product Specification Logic Products FEATURES • Common Address Inputs • True or complement data demultiplexing • Dual 1-of-4 or 1-of-8 decoding • Function generator applications

HY1C

Contextual Info: LS155 Dual 2-Line-To-4-Line Decoders/Demultiplexers LS156 FEATURES • ■ LOGIC DIAGRAM LS156 has open-collector outputs Applications: STRO BE 1G Dual 2-Line-to-4-Line Decoder Dual 1-Line-to-4-Line Demultiplexer 3-Line-to-8-Line Decoder 1-Line-to-8-Line Demultiplexer

LS155

Contextual Info: AVG Semiconductors_ DDi Technical Data Dual 1 of 4 Decoder/ Demultiplexer The LS155 is a high speed Dual one-of-four decoder/demul­ tiplexer. This device has two decoders with common two-bit Address inputs and separate gated Enable inputs. Decoder

LS155

Contextual Info: LS155*LS156 National Semiconductor LS155/LS155/LS155, 54LS156/DM54LS156/DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers General Description Features These TTL circuits feature dual 1-line-to-4-line demultiplex­ ers with individual strobes and common binary-address in­

Contextual Info: Dual 2-Line-To-4-Line Decoder/Demultiplexer With Three-State Outputs LS255 PIN-OUT DIAGRAM FEATURES • ■ OUTPUT CONTROL Three-state version of LS155 Applications: Dual 2-Line-to-4-Line Decoder Dual l-Line-to-4-Line Demultiplexer 3-Line-to-8-Line Decoder

74155 demultiplexer pin diagram and function table

Abstract: 74155 demultiplexer 74155 PIN DIAGRAM 74155 pin configuration 74ls155 pin configuration 74155 decoder LS155 74155 demultiplexer pin configuration decoder 74155 74155 signetics
Contextual Info: 74155, LS155 Decoders/Demultiplexers Dual 2-Line To 4-Line Decoder/Demultiplexer Product Specification Logic Products FEATURES • Common Address Inputs • True or complement data demultiplexing • Dual t-of-4 or 1-of-B decoding • Function generator applications

74155 demultiplexer pin diagram and function table

Abstract: 74155 pin configuration 74155 demultiplexer 74155 demultiplexer signetics 74155 demultiplexer pin configuration decoder 74155 74155 74155 decoder 74155 demultiplexer function table 74155 PIN DIAGRAM
Contextual Info: 74155, LS155 Signetics Decoders/Demultiplexers Dual 2-Line To 4-Line Decoder/Demultiplexer Product Specification Logic Products FEATURES • Common Address Inputs • True or complement data demultiplexing • Dual 1-of-4 or 1-of-8 decoding • Function generator applications

2936A

Abstract: ls155 LS156
Contextual Info: LS155 Dual 2-Line-To-4-Line Decoders/Demultiplexers LS156 FEATURES LOGIC DIAGRAM • LS 1 5 6 has open-collector outputs ■ A pplications: Dual 2 -L in e-to -4-L in e Decoder Dual 1 -Lin e-to -4-L ine D em ultiplexer m O U TP U T 1Y 0 O U TP U T 1Y1 3 -L in e-to -8-L in e Decoder

74155 demultiplexer pin diagram and function table

Abstract: 74155 pin configuration 74155 demultiplexer 74ls155 pin configuration 74155 decoder pin diagram of 74155 ttl 74155 74155 demultiplexer signetics 74155 PIN DIAGRAM 74155
Contextual Info: 74155, LS155 Signetics Decoders/Demultiplexers Dual 2-Line To 4-Line Decoder/Demultiplexer Product Specification Logic Products FEATURES • Common Address Inputs • True or complement data demultiplexing • Dual 1-of-4 or 1-of-8 decoding • Function generator applications

LS155

Abstract: 000014E
Contextual Info: AVG Semiconductors DDi Technical Data 155 LS155 LS155 Dual 1 of 4 Decoder/ Demultiplexer The LS155 is a high speed Dual one-of-four decoder/demul­ tiplexer. This device has two decoders with common two-bit Address inputs and separate gated Enable inputs. Decoder

74HC4096

Abstract: EQUIVALENT TIMER IC WITH CD 4060 rs flip-flop IC 7400 C4050A shiftregister PIPO C148A LS 7476 L1AA C4051A LS294
Contextual Info: Selection Guide C2MOS Logic TC74HC/HCT Series 2. High Speed CMOS Selection Guide GATE NAND HCOOA NOR AND OR INVERTER, BUFFER EXCLUSIVE OR/NOR SC HM ITT TRIGGER HC02A HC08A H C31A H C04A H C86A H C14A H C51A H C4049A M ULTI FUNCTION LEVEL SHIFTER HCTOOA HCT02A

sn74155

Abstract: LS156 SN54155 SN54156 SN54LS155A SN54LS156 SN74156 SN74LS155A SN74LS156 LS155A
Contextual Info: S N 5 41 55 , S N 5 4156, S N 54LS 155A , SN 54LS156, S N 7 4 1 5 5 , S N 7 4 1 5 6 , S N 7 4 L S 1 5 5 A , S N 7 4L S 1 5 B SDLS057 DUAL 2 LINE TO 4 LINE D EC O D ER S/D E M U LTIP LE XE R S MARCH 1974 - Applications: Dual 2-to 4-Line Decoder Dual 1-to 4-Line Demultiplexer

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

54LS155DMQB

Abstract: 54LS155FMQB 54LS155LMQB 54LS156DMQB DM54LS155J DM54LS155W DM74LS155M DM74LS155N LS155 LS156
Contextual Info: S E M IC O N D U C T O R tm LS155/DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers General Description Features These TTL circuits feature dual 1 -line-to-4-line d em ultiplex­ ers with individual strobes and com m on binary-address in­ puts in a single 16-pin package. W hen both sections are e n ­

Contextual Info: SG60R4 Schottky TTL • Over 180 LS Devices • ALS • FAST TOTAL TTL COMMITMENT «TOTAL • TTL Compatible Macrocell Arrays • RAMs • PROMs General Information TTL in Perspective proved speed — p o w e r product co m p ared to LS as a result o f ad vanced M O S A IC oxide isolated processing.

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

74LS155

Contextual Info: MOTOROLA SN54LS/LS155 SN54LS/74LS156 D E S C R IP T IO N — T h e S N 5 4 L S /7 4 L S 1 55 and S N 5 4 L S /7 4 L S 1 56 are high speed Dual 1-of-4 D ecoder/D em ultiplexers. These devices have tw o decoders w ith comm on 2-bit Address inputs and separate gated

T74LS155

Contextual Info: S G S-THONS ON D7E D I 7 ^ 2 3 7 DDlblOQ 3 I LOW POWER SCHOTTKY INTEGRATED CIRCUITS 6 T C - 1 6 2 2 9 . T -6 6 -2 1 -5 5 DUAL 1-OF-4 DECODER/DEMULTIPLEXER DESC RIPTIO N The TTL/MSI LS155/LS155 and T54LS156/ T74LS156 are high speed Dual 1-of-4 Decoder/De­

LS155

Abstract: demultiplexer truth table LS156 T74LS156 74 ls 155 demultiplexer
Contextual Info: in i ss DUAL 1-0F-4 DECODER/DEMULTIPLEXER DESCRIPTION The TTL/MSI LS155/LS155 and T54LS156/ T74LS156 are high speed Dual 1-of-4 Decoder/De­ multiplexers. These devices have two decoders with common 2-bit Address inputs and separate ga­ ted Enable inputs. Decoder “ a” has an Enable gate