74 AND GATES Search Results

Contextual Info: SIU54HC7074, SN 74 H C 70 74 6-SECTION M ULTIFUNCTION NAND. INVERT. NOR. FLIP FLOP CIRCUITS 028 31 , MARCH 1984-REVISED SEPTEMBER 1987 SN 54H C 7074 . . . JT PACKAGE SN 74H C 7074 . . . DW OR NT PACKAGE Contains D-type Flip-Flops w ith Preset and Clear, N A N D , NOR, and Inverter Gates

uart 8250

Abstract: LZ64 uart 8051 115200 2n7000 complement 8250 UART master touch
Contextual Info: APPLICATION NOTE 74 Application Note 74 DALLAS SEMICONDUCTOR Reading and Writing Touch Memories via Serial Interfaces I. INTRODUCTION For read operations all devices are satisfied with a 5kQ pull-up resistor to supply energy and to terminate the 1-W ire bus. Touch Memory devices based on non-vol­

Schmersal AZM 160

Abstract: Schmersal AZM 160 22 THERMAL Fuse m20 tf 115 c IEC 60947-5-1 limit switch EN 1088 schmersal interlock solenoid wiring diagram
Contextual Info: Safety in system: Protection for man and machine Main catalogue | Safety technology | Version 8.1 K.A. Schmersal GmbH & Co. KG Safety control systems Möddinghofe 30 D-42279 Wuppertal Phone: +49- 0 2 02-64 74-0 Fax: +49-(0) 2 02-64 74-100 E-Mail: info@schmersal.com

AN-363

Abstract: C1995 LS00 of ic 74 ls00 AN-363 national designing with ttl
Contextual Info: National Semiconductor Application Note 363 Walt Sirovy June 1984 54 74 series TTL has been used for more than a decade with excellent results and continues to be a standard choice for design engineers because of the wide performance range and system optimization possible from the different families available 54 74 logic comes in 8 different

JESD97

Abstract: STY80NM60N 80NM60N
Contextual Info: STY80NM60N N-channel 600 V, 0.030 Ω, 74 A, MDmesh II Power MOSFET Max247 Features Type VDSS @ TJmax RDS on max ID STY80NM60N 650 V < 0.035 Ω 74 A • The worldwide best RDS(on) in Max247 ■ 100% avalanche tested ■ Low input capacitance and gate charge

STY80NM60N

Abstract: 80NM60N
Contextual Info: STY80NM60N N-channel 600 V, 0.030 Ω, 74 A, MDmesh II Power MOSFET Max247 Features Type VDSS @ TJmax RDS on max ID STY80NM60N 650 V < 0.035 Ω 74 A • The worldwide best RDS(on) in Max247 ■ 100% avalanche tested ■ Low input capacitance and gate charge

STR G 6351

Abstract: str 6351 54ACT10 54ACTQ10 74ACT10 AC10 smd 3D5 3 PIN
Contextual Info: & March 1993 Semiconductor 54 AC/74 AC 10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The ’A C /’AC T10 contains three, 3-input N AND gates. • Ic e reduced by 50% on 5 4 A C /74 A C only ■ O utputs s o u rc e /s in k 24 mA ■ Standard M ilitary Drawing SMD

uart 8250

Abstract: 8250 uart 8250 uart datasheet programmable interval timer 8253 real time microprocessor 8253 applications 100 ohm POT .25W interfacing 8051 with eprom and ram zener diode 1N5232 8253 Programmable Interrupt Controller microprocessors interface 8253 "Real Time Clock"
Contextual Info: APPLICATION NOTE 74 Application Note 74 Reading and Writing iButtons via Serial Interfaces I. INTRODUCTION An iButtonTM is a chip housed in a stainless steel enclosure. The electrical interface is reduced to the absolute minimum, i.e., a single data line plus a ground reference. The energy needed for operation is either “stolen”

uart 8250

Abstract: LZ64 8250 uart RS232-specification zener diode 1N4742 8250 uart rxd 8250 uart datasheet DS1982 DS1986 DS1991
Contextual Info: APPLICATION NOTE 74 Application Note 74 Reading and Writing iButtons via Serial Interfaces I. INTRODUCTION An iButtonTM is a chip housed in a stainless steel enclosure. The electrical interface is reduced to the absolute minimum, i.e., a single data line plus a ground reference. The energy needed for operation is either “stolen”

C574Q

Abstract: ED-37
Contextual Info: Military Standard FIFO s 64x4 64x5 C ascad ab le & Standalone Memory C57401 57401 C57401A 5 74 01 A C57402 5 7402 C 5 74 02 A 57402A Features/Benefits Description • • • • • The C/57401/1A and C57402/2A are “fall through” high-spead First-In First-Out FIFO memories organized 64 words by 4 bits

74ALS136

Abstract: 74as136
Contextual Info: SN 54A LS136, S N 54A S136, SN 74 A LS1 36, S N 74 A S136 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS D 2 8 3 7 , M A R C H 1 9 8 4 - R E V IS E D M A Y 1 9 8 6 P ackage O ption s Include P lastic "S m a ll O u tlin e " Packages, C eram ic Chip Carriers, and S tandard

MA161

Contextual Info: DN74LS54 LS T T L DN74LS Series DN74LS54 74 LS ^ 4 - wide AND-OR-INVERT Gates • Description DN74LS54 contains four 2-input and four 3-input AND-ORINVERT gates. ^0^ ■ Features • • • • Low power consumption Pa = 4.5mW typical High speed ( tpa = 12ns)

Contextual Info: SN S4F10, S N 74 F 10 TRIPLE 3-INPUT POSITIVE-NANO GATES 02932, MARCH 1987-REVISED JANUARY 1989 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs SN 54F10 . . . J PACKAGE SN74F10 . . . D OR N PACKAGE

074d

Contextual Info: Semiconductor February 1993 54 A C /74 AC 11 Triple 3-Input AND Gate General Description Features The ’AC11 contains three 3-input AND gates. • ■ ■ ■ Logic Symbol Ice reduced by 50% Outputs source/sink 24 mA Standard Military Drawing SMD ’AC11: 5962-87611

Contextual Info: LS TTL DN74LS Series DN74 LS21 DN74LS21 t>10 74.^^1 Dual 4 -input P ositive AND Gates • Description DN74LS21 contains two 4-input positive isolation AND gate circuits. ■ • • • P-1 Features Low power consumption Pj = 8.5 mW typical High speed (tpd = 9ns typical)

QL3004-1PF100C

Abstract: QL3004 QL3004-1PL68C QL4009-1PL84C pASIC3
Contextual Info: QL3004 - pASIC 3 FPGATM 4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density last updated 5/17/2000 QL3004 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights High Performance & High Density • 4,000 Usable PLD Gates with 74 I/Os

SOT886

Abstract: BGA Package 0.35mm pitch SOT891 wcsp sot886-1 SOT-902 sot665
Contextual Info: NXP MicroPak and MicroPak II packages for single-, dual-, and triplegate logic functions World’s smallest leadless logic packages MicroPak and MicroPak II packages are the world’s smallest packages for single-, dual-, and triple-gate logic. They are 65% - 74% smaller than their PicoGate equivalents and offer a larger

TTL 7411

Abstract: TTL 7410 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 74LS10 pin configuration 7410 pin configuration 74LS10 function table 7411 ttl pin configuration of 7410 LS 7411
Contextual Info: Signetics I 74-10, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6m A 74LS 10 10ns 1.2m A 74S 10 3ns 12m A 7411

PO74G02A

Contextual Info: PO54G02A, PO74G02A www.potatosemi.com QUADRUPLE 2-INPUT POSITIVE-NOR GATES 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: . Patented technology . Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C . Operating frequency up to 900MHz with 2pf load

DN74LS08

Contextual Info: i_ o T T L D N 7 4 L S S e r i e s DN74LS08 DN74LS08 Oiv>74<-Sci> ? Quad 2-input Positive AND Gates • Description DN74LS08 contains four 2-input positive isolation AND gate circuits. P-1 ■ Features • • • • Low power consumption Pd = 17mW typical

Contextual Info: SN54F36, SN74F36 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2932, MARCH 1987-REVISED JANUARY 1989 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mll DIPs SN 54F36 . . . J P A C KA G E SN 74 F36 . . . D OR N P A C K A G E

pin diagram for all 74 series ttl gates

Abstract: TTL 74 series DM7423N DM7413N DM7425N 74 series logic circuits DM7400N 74 series logic gates SN7413N DM7410N
Contextual Info: National Sem iconductor Integrated Circuits—74 Series D E S C R IP T IO N Series 74 integrated circuits are designed and characterised fo r high-speed, general-pdrpose digital applications where high DC noise margin and relatively low power dissipation are im portant

60c31

Abstract: 74HC74 74HCT-Logic 80C31HB 27C2M EPROM 27C256 interface hardware 74HC cmos family spec
Contextual Info: CHAPTER 7 80C51 Family Designing with the 80C51BH CMOS EVOLVES The original CMOS logic families were the 4000-series and the 74C-series circuits. The 74C-series circuits are functional equivalents to the correspondingly numbered 74-series TTL circuits, but have CMOS logic levels and

SN54F260

Abstract: F260 texas 54F260
Contextual Info: SN54F260, SN74F260 DUAL 5-INPUT POSITIVE NOR GATES D3214, J A N U A R Y 1989 • SN 54 F26 0 . . . J P A C K A G E SN 74 F26 0 . . . D OR N P A C KA G E Package Options Include Ceramic Chip Carriers and Flat Packages in Addition to Plastic and Ceramic DIPs