74ACT10 Search Results

74AC390

Abstract: 74AC54D 74ac841 74AC163 74AC393 74AC245 74AC670 74ac109 74AC623 74ACT640
Contextual Info: SELECTION GUIDE TC74AC/ACT Series Selection Guide NAND 74AC00 74ACTOO NOR 74AC02 74ACT02 AND 74AC08 74ACT08 OR 74AC32 74ACT32 INVERTER, BUFFER 74AC04 74ACT04 EXCLUSIVE OR 74AC86 74ACT86 GATE SCHMITT TRIGGER BUS BUFFER BUFFER BUS TRANSCEIVER 74AC10 74ACT10

master slave jk flip flop

Abstract: ECL D flip flop Flip Flop DIP Flip flop JK cmos 74lvt16374 d flip flop d type flip flop flip flop flip flop circuit flip flop circuit type D
Contextual Info: Logic Products by Function Flip-Flop Products Logic Product Family Product Description Package Voltage Node 74ACT109 FACT ACT Dual JK Positive Edge-Triggered Flip-Flop DIP SOIC TSSOP 5 DM74LS73A Bipolar-LS Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary

Contextual Info: Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Tf x a s In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC H S282 IS- » 2 1JÎK IC f*ÎR • 3 4 1 1 • IO Dual “J-K” Flip-Flop with Set and Reset F /F 1 CD54/74AC/ACT109 - Positive-Edge-Triggered J, K

Contextual Info: SGS-THOMSON 74ACT10 M 0 gl3 l[LI(3ra [S!]D(BS TRIPLE 3-INPUT NAND GATE PRELIM IN ARY DATA . HIGH SPEED: tPD = 6.5 ns (TYP. at Vcc = 5V . LOW POWER DISSIPATION: Ice = 4 |xA (MAX.) at TA = 25 °C . COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN), V il = 0.8V (MAX)

74AC109

Abstract: 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC
Contextual Info: Revised November 1999 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock

S35R2

Abstract: 1278n 74aC-aCT109 CD541 j8332 RCA
Contextual Info: HARRIS SEMICOND SECTOR 37E D • 4302271 D025411 6 *HAS _ Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Information 07 Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K

74AC109

Abstract: 74AC109PC 74AC109SC 74AC109SJ 74ACT109 M16A M16D
Contextual Info: S H IU D Revised O ctober 1998 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LO W input to Cp Clear sets Q to LOW level T h e AC /AC T109 consists of two_ high-speed com pletely independent transition clocked JK flip-flops. The clocking

Contextual Info: 43G2271 D G 2 S 4 H 37E D HARRIS SEMICOND SECTOR _ ñ *HAS Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Information T^fc-or?- 0 7 Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K

Contextual Info: 53 National ÆM Semiconductor 54AC/74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The 'AC/'ACTIO contains three, 3-input NAND gates. • Icc reduced by 50% on 54AC/74AC only ■ Outputs source/sink 24 mA ■ Standard Military Drawing SMD

948F

Abstract: MC74AC109 MC74AC109D MC74AC109N MC74ACT109 MC74ACT109D MC74ACT109N
Contextual Info: MC74AC109, 74ACT109 Dual JK Positive Edge−Triggered Flip−Flop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.

Contextual Info: AC1017 • ACT1017 54AC/74AC1017 • 54ACT/74ACT1017 16 x 16 Parallel Multiplier Description Connection Diagram The 'AC/’ACT1017 is a high-speed, low power 16 x 16-bit parallel multiplier that is ideally suited for real-time digital signal processing applications.

Contextual Info: s e m ic o n d u c t o r Revised November 1999 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two_ high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock

Contextual Info: AC109 • ACT109 54AC/74AC109 • 54ACT/74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flipflops. The clocking operation is independent of

615162

Contextual Info: NATIONAL SEMICOND L06IC blE b 5 D 1 1 2 2 00747flb bTb « N S C 1 J> T - H L 'O T - 0 7 03 National ÆM Semiconductor 54AC/74AC109 • 54ACT/74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’AC /’ACT109 consists of two high-speed completely

74AC109

Abstract: 74AC109MTC 74ACT109 74AC109SC 74AC109SJ 74ACT109PC 74ACT109SC
Contextual Info: 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop tm Features General Description • ICC reduced by 50% The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the

74AC10

Abstract: 74AC 74AC10MTC 74AC10PC 74AC10SC 74AC10SJ 74ACT10 74ACT10PC 74ACT10SC
Contextual Info: Revised February 2005 74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The AC/ACT10 contains three, 3-input NAND gates. • ICC reduced by 50% on 74AC only ■ Outputs source/sink 24 mA Ordering Code: Order Number Package Number 74AC10SC

Contextual Info: Technical Data „ , CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Information Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features:

Contextual Info: Technical Data , CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Advanced Informaron Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features: • Buffered inputs

sop65p640

Abstract: SOP65
Contextual Info: 74AC10, 74ACT10 Triple 3-Input NAND Gate Features General Description • ICC reduced by 50% on 74AC only The AC/ACT10 contains three, 3-input NAND gates. ■ Outputs source/sink 24mA Ordering Information Order Number Package Number 74AC10SC 74AC10SJ 74AC10MTC

ZD302

Contextual Info: 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to C q Clear sets Q to LOW level T h e AC /AC T109 consists of two_ high-speed com pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall tim es of th e clock

Contextual Info: M O TO R O LA MC74A C 109 74ACT109 D ual J K P o sitiv e Ed ge-Trig gered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of tw o high-speed completely Independent transition clocked JK flip-flops. The clocking operation is independent o f rise and

Contextual Info: March 1993 Semiconductor 54AC/74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The ’AC /’ACT10 contains three, 3-input NAND gates. • Ice reduced by 50% on 54AC/74AC only ■ Outputs source/sink 24 mA ■ Standard Military Drawing SMD

Contextual Info: Revised October 1998 j,f > i '' ^ : 3? •? » 74AC10 • 74ACT10 Triple 3-Input NAND Gate General Description Features The AC/ACT10 contains three, 3-input NAND gates. ■ lc c reduced by 50% on 74AC only ■ Outputs source/sink 24 mA Ordering Code: Order Number

Contextual Info: AC1010 • ACT1010 54AC/74 AC 1010 • 54ACT/74ACT1010 16 x 16 Parallel Multiplier/Accumulator Description Connection Diagrams The ’AC/’ACT1010 is a high-speed, low-power 16 x 16 bit parallel m ultiplier with a 35-bit accumulator that is ideally suited for real-time