PASIC3 Search Results

vhdl code for time division multiplexer

Abstract: vhdl projects abstract and coding radix delta ap 796n Controller C384 vhdl code for multiplexer SIGNAL PATH designer vhdl code for time division multiplexer abstract
Contextual Info: Designing with FPGAs t An Introduction to Cypress's pASIC380 Family Warp3 of FPGAs and the Design Tool simulation, and device specifics required in the deĆ Introduction sign description are discussed. Field Programmable Gate Arrays FPGA borrow the sea of gates concept from the gate array semicusĆ

programmer manual EPLD cypress

Abstract: pASIC380 programming manual EPLD CY7C383A GAL programmer schematic
Contextual Info: filename: Tuesday, August 11, 1992 Revision: October 9, 1995 pASIC380 Family UltraLogict Very High Speed CMOS FPGAs D Robust routing resources Features D Very high speed D D D D D D D Ċ Loadable counter frequencies greater than 150 MHz Ċ ChipĆtoĆchip operating frequencies

208pin PQFP

Abstract: QL3025 pci arbiter
Contextual Info: PCI ARBITER                               MARIA GEORGE Customer Engineer ABSTRACT This paper will discuss the design of a PCI Arbiter implemented into Quicklogic’s pasic3

PQFP 176

Contextual Info: Military Plastic pASIC 3 Family 60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density last updated 5/4/2000 Military pASIC 3 - 3.3V Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features High Performance and High Density Total of 180 I/O pins

CI 3060 elsys

Abstract: 84-PIN QL3012 QL3025 QL3040 QL3060 QL3060-1PQ208M
Contextual Info: Military Plastic pASIC 3 Family 60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density Military pASIC 3 - 3.3V Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features High Performance and High Density Total of 180 I/O pins •

application of programmable array logic

Abstract: 4000 CMOS CMOS 4000 digital clock using logic gates FLASH370 pASIC380
Contextual Info: PRESS RELEASE CYPRESS EXPANDS FPGA OFFERING WITH 8,000-GATE DEVICES Highest Performance FPGAs Offer Full PCI Compliance For All Speed Grades SAN JOSE, Calif., February 27, 1995 - Cypress Semiconductor Corporation today introduced 8000-gate versions of its speed-leading pASIC380 family of fieldprogrammable gate arrays. The new CY7C387A and CY7C388A FPGAs are fully

programmer manual EPLD cypress

Contextual Info: l l lt fM d l l l t? . I U t? 5 U d y , M U y U 5 > l I I , ItKfcS Revision: Tuesday, June 28,1994 pASIC380 Family F/ CYPRESS Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz

Contextual Info: QL3004 4,000UsablePLDGatepASIC 3FPGA CombiningHighPerformance a«i/HighDensity Last Updated August 6, 1999 pASIC3 HIGHLIGHTS . 4,000 usable PLD gates, 82 I/O pins 5 HighPerformanceandHighDensity -4,OOOUsablePLDGateswith76I/Os -

pasic380

Abstract: Cypress Semiconductor CY3125 CY3146 synopsys
Contextual Info: CY3146: April 19, 1995 Revision: September 14, 1995 PRELIMINARY Features CY3146 Synopsys Design Software Kit for pASIC380t Ordering Information CY3146 Synopsys pASIC380 FPGA Design Software SunĆbased includes: 3½Ćinch disk Sun version pASIC FPGA Synopsys Library

sdram controller

Abstract: sdram Dynamic RAM Controller controller sdram free
Contextual Info: 1 SDRAM Controller SDRAM Controller VENDOR QuickLogic Corp 1277 Orleans Drive Sunnyvale, CA 94089 USA Tel. 408 990 4000 Fax (408) 990 4040 Email info@quicklogic.com WWW http://www.quicklogic.com December 1999 OVERVIEW The SDRAM Controller bridges between standard bus

CY7C381P

Abstract: CY7C381P-0JC CY7C381P-XJC CY7C381P-XJI CY7C382P CY7C383A CY7C385P 100-Pin CPGA Package Pin-Out Diagram
Contextual Info: CY7C381P CY7C382P CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns • Unparalleled FPGA performance for counters, data path, state machines,

CY7C3381A

Abstract: CY7C3381A-0JC CY7C3381A-0JI CY7C3381A-XJC CY7C3382A CY7C3384A CY7C3385A 00252-B
Contextual Info: CY7C3381A CY7C3382A CYPRESS Features • Very high speed — Loadable counter frequencies greater than SO MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithmetic, and random logic

frws 5-4

Abstract: CY7C381-0JI C3816 G68 Package vhdl code for lte channel coding CY7C381 CY7C382 7c381 C381-9 C3812
Contextual Info: ¡iiö i id in tJ . iv iu iiu c iy , M u y u t ji i / , Revision: Wednesday, March 16,1994 ¥ CY7C381 CY7C382 cypress Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

Contextual Info: tvjooim. iviunuay, oepiariiuei ¿u, i»»o Revision: Tuesday, May 10,1994 r# CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 120 MHz — Input + logic cell + output delays

Contextual Info: Revision: Thursday, September 24,1992 MUR 23 1993 PRELIMINARY CYPRESS s7-W '" SEMICONDUCTOR Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

Contextual Info: CY7C3381A CY7C3382A 5r CYPRESS Features • Very high speed — Loadable counter frequencies greater than SO MHz — Chip-to-chip operating frequencies up to 60 MHz UltraLogic 3.3V High Speed IK Gate CMOS FPGA — PC and workstation platforms Functional Description

Contextual Info: QL4009 9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM Last Updated: October 25 1999 QuickRAM HIGHLIGHTS … 9,000 usable PLD gates, 82 I/O pins High Performance and High Density - 9,000 Usable PLD Gates with 82 I/Os - 300 MHz 16-bit Counters, 400 MHz Datapaths, 160+ MHz FIFOs

Contextual Info: QL3004 4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Last Updated August 31, 1999 4 pASIC 3 HIGHLIGHTS … 4,000 usable PLD gates, 82 I/O pins High Performance and High Density -4,000 Usable PLD Gates with 82 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR Very High Speed 2K 6K Gate CMOS FPGA — Waveform simulation with back annotated net delays — PC and workstation platforms • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies

Contextual Info: Revision: Monday, December 14,1992 a* CY7C381 CY7C382 PRELIMINARY H v p p rc c — Very High Speed IK 3K Gate CMOS FPGA SEMICONDUCTOR Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies

asynchronous fifo vhdl

Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024
Contextual Info: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com

TEMIC PLD

Abstract: EPM9000 Temic ulc EPM5000
Contextual Info: ULC–FPGA Conversions Ultimate Logic Conversion – Introduction Description FPGAs and PLDs are excellent tools for design development and lower-volume production. They provide a quick design cycle for fast time to market, low development costs and low risk. In higher-volume

architecture of cypress FLASH370 device

Abstract: cypress FLASH370 programming architecture of cypress FLASH370
Contextual Info: PRESS RELEASE CYPRESS ADDS NEW SYNTHESIS CAPABILITY TO $99 WARP2 Leading VHDL Programming Tool Now Supports All Cypress PLDs and CPLDs SAN JOSE, Calif., April 22, 1996 - Cypress Semiconductor Corp. today introduced Release 4 of its highly popular, $99 VHDL-based Warp2

architecture of cypress FLASH370 device

Abstract: FLASH370
Contextual Info: PRESS RELEASE CYPRESS ADDS NEW SYNTHESIS CAPABILITY, FPGA SUPPORT TO $99 WARP2 Leading VHDL Programming Tool Now Supports All Cypress PLDs, CPLDs, and FPGAs SAN JOSE, Calif., April 22, 1996 - Cypress Semiconductor Corp. today introduced Release 4 of its highly popular, $99 VHDL-based Warp2