54LS114 Search Results

Contextual Info: M M O T O R O L A Military 54LS114A D u a l J -K Flip-Flop W ith Preset, C o m m o n C le ar and C o m m o n C lo c k MIL-M-38510/30105 T h e 5 4 L S 1 1 4 A o ffe rs c o m m o n clock a n d c o m m o n clear inputs and in d ivid u al J, K, and set inputs. Th e se m o n o lith ic dual flip -flo p s are

Contextual Info: 8 < > M ilitary 54LS114A MOTOROLA Dual J -K Flip-Flop W ith P reset, Common C lear and Com m on C lock MPO MIL-M-38510/30105 unw The 54LS114A offers common clock and common clear inputs and individual J, K, and set Inputs. These monolithic dual flip-flops are

LS114

Contextual Info: ^ National Semiconductor 54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’L S 1 14 features individual J, K and set inputs and com­ mon clock and common clear inputs. When the clock goes HIGH the inputs are enabled and data will be accepted. The

SN54LS114A

Abstract: SN54S114 SN74 SN74LS114A SN74S114A LS114
Contextual Info: 54LS114A, SN54S114, SN74LS114A, SN74S114A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK MARCH 1973 —R EV ISED MARCH 1988 SN 54LS114A . SN 54S114 SN 74LS114A . SN 74S114A • Fully Buffered to Offer Maximum Isolation

Contextual Info: M M O T O R O M ilitary 54LS114A L A Dual J -K Flip-Flop W ith P reset, Com m on C lear and Com m on C lock M MIL-M-38510/30105 P O H U M The 54LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are

LS114

Abstract: 54LS114 54LS114DMQB 54LS114FMQB 54LS114LMQB C1995 E20A J14A W14B
Contextual Info: 54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’LS114 features individual J K and set inputs and common clock and common clear inputs When the clock goes HIGH the inputs are enabled and data will be accepted The

Contextual Info: 54LS114A, SN54S114, SN74LS114A, SN74S114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK M A R C H 1973 — R E V ISE D M A R C H 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance SN 54LS114A . SN 54S114

Contextual Info: 54LS114A. SN54S114, SN74LS114A, SN74S114A DUAL J K NEGATIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK _ MARCH 1973 —REVISED MARCH 1988 • Fully B u ffe re d to O ffe r M a x im u m Isolation

74s188 programming

Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
Contextual Info: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE

74LS115

Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
Contextual Info: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

74LS114

Abstract: 74ls114d 74S114DC
Contextual Info: 114 C O N N E C T IO N D IA G R A M PINOUT A •01 ! .54S/74S114 54LS/74LS114 D I / ö H p 003 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP c5{T 1 4 ] Vcc k , T (With Common Clocks and Clears K, C P J i CO S pi Qi Qi Ji[ T n ] cp m D E S C R IP T IO N — The '114 features individual J, K and set inputs and com­

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

ay-5-1012

Abstract: ali m 3329 PROCESSOR ALI 3329 ali 3329 b ali 3329 SN74188 sn74s188 str 52100 SN7452 replacement of bel 187 transistor
Contextual Info: GENERAL INFORMATION lie of Contents • Alphanumeric Index • Selection Guides • Glossary INTERCHANGEABiliTY GUIDE MOS MEMORIES TTL MEMORIES ECl MEMORIES MICROPROCESSOR SUMMARY 38510/MACH IV PROCUREMENT SPECIFICATION JAN Mll-M-38510 INTEGRATED CIRCUITS

SN54LS114A

Abstract: SN54S114 SN74 SN74LS114A SN74S114A
Contextual Info: 54LS114A, SN54S114, SN74LS114A, SN74S114A DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK SDLS010 _ • Fully Buffered to Offer Maxim um Isolation from External Disturbance • Package Options Include Ceramic Carriers

2650B

Abstract: wf vqc 10d alu 9308 d Signetics 2650 SN52723 2650 cpu 82S103 pipbug Signetics NE561 cd 75232
Contextual Info: flcnCTICf ßii>ouiR/mos fflICROPROCEÍSOR DATfl mnnuni SIGNETICS reserves the right to make changes in the products contained in this book in order to improve design or performance and to supply the best possible products. Signetics also assumes no responsibility for the

1n52408

Abstract: 1N52428 zener SFC2311 78M12HM 21L02A 54175 IRS 9530 transistor 10116dc BB105G 962PC
Contextual Info: Contents Fairchild Semiconductors Ltd. Solid State Scientific Inc. Diodes Ltd. Thomson C. S. F. B Ashcroft Electronics Ltd. Sprague Electric UK Ltd. Precision Dynamic Corp. B&R Relays Schrack Relays Heller mann Electric B Foreword We are pleased to present the latest edition of the BARLEC Catalogue, which

FMK2

Abstract: 74LS114 54LS114DM 54S114DM 54S114FM 74LS114DC 74LS114FC 74LS114PC 74S114DC 74S114FC
Contextual Info: 114 CONNECTION DIAGRAM PIN O U T A 54S/74S114 54LS/74LS114 •Öl / f D \ t O 3 DUAL JK N E G A TIV E E D G E -T R IG G E R E D F L IP -F L O P Cd {T W ith C om m on C locks and Clears Ï 3 Vcc ETL K)[T Ki C P J i CD SD1 Qi Qi Ji |T n jc p Ü]K2 Soi[T DESCRIPTION— The '114 features individual J, K and set inputs and com­

100414DC

Abstract: 5401DM Fairchild dtl catalog fsa2719m 4727BPC FCM7010 FCM7004 937DMQB fairchild rtl FSA2501
Contextual Info: FAIRMONT ELECTRONICS PTY. LTD. TE L.48-6421 4 8 -6 4 8 1 /2 /4 C AB LES ' FAIRTRONICS' C R A IG H A L L T E L E X 8-3227 S A . P O .BOX 41102, C R A IG H A LL 2024. I ouani v-ox 39! 262Bramley 2018 FAIRCHILD 464 Ellis Street, M ountain View, C alifornia 94042

74LS114

Abstract: cpj2 8 pin dip j k flipflop ic
Contextual Info: ' NATIONAL SENICOND -CLOCICJ OSE D | b SO llS S 00^37^1 7 | 114 ~ F m -0 7 -0 7 CO NNECTIO N DIAGRAM PINOUT A 54S/74S114 54LS/74LS114 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP c 5 [T ETL Ki T (With Common Clocks and Clears K i CP J t CO Sd ) Qi Ji [ T Oi

74LS114A

Contextual Info: TYPES 54LS114A, SN54S114, SN74LS114A, SN74S114 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK REVISED DECEMBER 1983 Fully Buffered to O ffer M axim um Isolation fro m External Disturbance S N 54L S 114A , S N 5 4 S 1 1 4 . . . J OR W PACKAGE

sn55470

Abstract: 7544-1 transistor SN75326 SN7401 SN75426 54175 SN75270 SN55450 sn75493 National Semiconductor Linear Data Book
Contextual Info: The Interface Circuits Data Book for Design Engineers First Edition IM P O R T A N T NO TICES Texas Instruments reserves the right to make changes at any tim e in order to im prove design and to supply the best product possible. T l cannot assume any responsibility for any circuits shown or