4FLSBL75 Search Results

4N2b

Abstract: 80C288
Contextual Info: INTEL CORP UP/PRPHLS bäE D • 4flSbl75 013270^ 3^5 in te l 80C186XL/80C188XL 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS ■ Low Power, Fully Static Versions of 80C186/80C188 ■ Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode

Contextual Info: in te l 28F020 2048K 256K x 8 CMOS FLASH MEMORY Flash Electrical Chip-Erase — 2 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 jas Typical Byte-Program — 4 Second Chip-Program 100,000 Erase/Program Cycles 12.0V ± 5 % Vpp High-Performance Read

Contextual Info: ^ EXUKDTT [PIRilMlG inte* 87C196KT/87C196KS 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER Automotive —40°C to + 125°C Ambient High Performance CHMOS 16-Bit CPU Up to 32 Kbytes of On-Chip EPROM Up to 1 Kbyte of On-Chip Register RAM Up to 512 Bytes of Additional RAM

Contextual Info: in te i ADVANCE INFORMATION 28F016XS 16-MBIT 1 MBIT x 16, 2 MBIT x 8 SYNCHRONOUS FLASH MEMORY • Effective Zero Wait-State Performance up to 33 MHz — Synchronous Pipelined Reads ■ SmartVoltage Technology — User-Selectable 3.3V or 5V V cc — User-Selectable 5V or 12V Vpp

Contextual Info: Ä M Ä K I I 0 M F @ [^ O ii]Ä ¥ 0 ® M VS28F016XS, MS28F016XS 16-MBIT 1 MBIT x 16, 2 MBIT x 8 SYNCHRONOUS FLASH MEMORY • VS28F016XS 40°C to +125°C — QML Certified — SE2 Grade ■ 0.25 MB/sec Write Transfer Rate ■ MS28F016XS 55°C to 125°C

Contextual Info: intJ. 2-MBIT 128K x 16, 256K x 8 LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY 28F200BL-T/B, 28F002BL-T/B m Low Voltage Operation for Very Low Power Portable Applications — Vcc = 3.0V-3.6 V • Automatic Power Savings Feature — 0.8 mA Typical Ice Active Current in

Contextual Info: INTEL CORP UP/PRPHLS bflE D • MfiBbl7S 16b in t e * 87C51 /80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C 51/80C 51B H /80C 51B H P /80C 31B H *S ee Table 1 fo r Proliferation Options High Perform ance CHMOS EPROM 5 Interrupt Sources

Contextual Info: in te i 1-MBIT 128K X 8 BOOT BLOCK FLASH MEMORY 2 8 F 0 0 1 B X -T /2 8 F 0 0 1 B X -B /2 8 F 0 0 1 B N -T /2 8 F 0 0 1 B N -B • High-Integration Blocked Architecture — One 8 KB Boot Block w/Lock Out — Two 4 KB Parameter Blocks — One 112 KB Main Block

Contextual Info: A B W A N O B O N IP O R Q W O Q N in te i 82091AA ADVANCED INTEGRATED PERIPHERAL AIP • Single-Chip PC Compatible I/O Solution for Notebook and Desktop Platforms: — 82078 Floppy Disk Controller Core — Two 16550 Compatible UARTs — One Multi-Function Parallel Port

008 cow 734

Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining

Contextual Info: in te i 0 M F [ i3 [m Y 0 N 80960CF-33, -25,-16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • S o c k e t and O b jec t C o d e C o m p atib le w ith 8 0 96 0C A • T w o In s tru c tio n s /C lo c k S u stain ed E xecu tion • F ou r 59 M b y te s /s D M A C h an n els w ith D ata Chaining

Contextual Info: PRODUCT PREVIEW Smart5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT 28F200B5, 28F400B5, 28F800B5 • SmartVoltage Technology — Smart5™ Flash: 5V Reads, 5V or 12V Writes — Increased Programming Throughput at 12V V pp ■ Very High-Performance Read — 2-, 4-Mbit: 60 ns Access Time

hall marking code A04

Abstract: INTELDX4 write-through YSS 928
Contextual Info: INTEL486 PROCESSOR FAMILY • lntelDX4TM P ro c e s s o r — Up to 100-MHz Operation -Speed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant I/O Buffers

80A51AH

Abstract: Intel 8051 20 MHz MCS-51 8031AH
Contextual Info: in tj, 8031AH/8051AH 8032AH/8052AH MCS 51 NMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS Automotive m High Performance HMOS Process • Bit-Addressable RAM ■ Internal Timers/Event Counters ■ 2-Level Interrupt Priority Structure ■ Programmable Full Duplex Serial

Contextual Info: ß R IH L D ß ilD IM D O T r in te i 80960JD EMBEDDED 32-BIT MICROPROCESSOR Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is 2x the Bus Clock — Load/Store Programming Model

FDS 4468

Abstract: HBT 01 - 04G INTEL 486 sx sl pinout 240950 JVC 4580 fds 4418 TOT - 4301 INTEL DX4 241199 Intel DX4TM
Contextual Info: intj, INTEL486 PROCESSOR FAMILY • Write-Back Enhanced lntelDX4™ Processor — Up to 100-MHz Operation — Speed-Multiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Write-Back Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant

8096 microcontroller

Abstract: 8096 microcontroller architecture 8096
Contextual Info: fp ^ iy iM O N ]* ? 8XC196KB ADVANCED 16-BIT CHMOS MICROCONTROLLER ROMIess OR ROM Automotive • —40°C to + 125°C Ambient ■ 232 Bytes of On-Chip Register RAM ■ 8 Kbytes of On-Chip ROM Optional ■ High-Performance CHMOS Process ■ Register-to-Register Architecture

8741a

Abstract: UPI-41
Contextual Info: 8741A UNIVERSAL PERIPHERAL INTERFACE 8-BIT MICROCOMPUTER • 8-Bit CPU plus ROM, RAM, I/O, Timer and Clock in a Single Package ■ Fully Compatible with All Microprocessor Families ■ One 8-Bit Status and Two Data Registers for Asynchronous Slave-toMaster Interface

SAL 41B

Abstract: 8088 instruction set CTX 12S RD smd lm 398- SAMPLE AND HOLD
Contextual Info: Ä in te i I M K l l O M I F iO M A T O ! * ! M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Low Power, Full Static Version of M80C186 ■ Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

G175

Abstract: 234T0 82439HX CH340
Contextual Info: INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER TXC • ■ ■ ■ ■ Optional Error Checking and Correction (ECC) Supports All 3V Pentium Processors Dual Processor Support PCI 2.1 Compliant Integrated Second-Level Cache Controller — — — — — —

intel PLD

Contextual Info: INTEL CORP UP/PRPHLS . • i n t g MME D ■ - . MÔSbl75 0101313 5 I ■ ITLl ' p ftg y o m M ? l " P i - 6 - 1^ - 27960CX PIPELINED BURST ACCESS 1M (128K x 8) CHMOS EPROM Pipelined Addressing fo r Optimal Bus Bandwidth on 80960CA — N ext Addressing Overlaps Last Data

Contextual Info: INTEL CORP UP/PRPHLS bflE » • 4ßSbl75 D131134 TTS ■ ITL1 j n + J 809XBH/839XBH/879XBH COMMERCIAL/EXPRESS HMOS MICROCONTROLLER ■ 879XBH: an 809XBH with 8 Kbytes of On-Chip EPROM ■ 839XBH: an 809XBH with 8 Kbytes of On-Chip ROM 232 Byte Register File

d5017

Abstract: schematic diagram 555 PAM 82820 mch chip 8-pin H049 obd usb api 4st 03 82820 GAR7 H027 MLT 22 542
Contextual Info: intei Intel 820 Chipset: 82820 Memory Controller Hub MCH Datasheet November 1999 Order Number: 290630-001 Mfl2bl75 GEGTTlb Ö5Ö • Intef* 82820 MCH intel. Information in this docum ent is provided In connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

270816

Abstract: 270901 80C54
Contextual Info: irrte! SbE D 4ñ2bl7S OllbblO 7Hb M I T L l 87C54/80C54 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES INTERNAL PROGRAM MEMORY 87C54/80C54—3.5 MHz to 12 MHz, VCc = 5V + 20% 87C54-1/80C54-1—3.5 MHz to 16 MHz, Vcc = 5V±20% 87C54-L/80C54-L—3.5 MHz to 8 MHz, Vcc = 3.3V ± 0.3V