402BL75 Search Results

Contextual Info: in te l 28F020 2048K 256K x 8 CMOS FLASH MEMORY Flash Electrical Chip-Erase — 2 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 jas Typical Byte-Program — 4 Second Chip-Program 100,000 Erase/Program Cycles 12.0V ± 5 % Vpp High-Performance Read

Contextual Info: P W iy iM D K M W in tJ . 87C51/80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C51/80C51BH/80C51BHP/80C31BH "See Table 1 for Proliferation Options High Performance CHMOS EPROM 5 Interrupt Sources 24 MHz Operation Programmable Serial Port

Contextual Info: ^ EXUKDTT [PIRilMlG inte* 87C196KT/87C196KS 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER Automotive —40°C to + 125°C Ambient High Performance CHMOS 16-Bit CPU Up to 32 Kbytes of On-Chip EPROM Up to 1 Kbyte of On-Chip Register RAM Up to 512 Bytes of Additional RAM

Contextual Info: I P ^ iU ö Ä Ä f in te i 28F008SA 8-MBIT 1-MBIT x 8 F la s h F ile T M MEMORY Extended Temperature Specifications Included High-Density Symmetrically Blocked Architecture — Sixteen 64-Kbyte Blocks Very High-Performance Read — 85 ns Maximum Access Time

Contextual Info: in tj, 8XC196KC/8XC196KC20 COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER 87C196KC—16 Kbytes of On-Chip OTPROM 83C196KC—16 Kbytes ROM 80C196KC—ROMIess • 16 and 20 MHz Available ■ Dynamically Configurable 8-Bit or 16-Bit Buswidth ■ 488 Byte Register RAM

Contextual Info: intJ 82078 64 PIN CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER — Selectable Boot Drive — Standard IBM and ISO Format Features — Format with Write Command for High Performance in Mass Floppy Duplication • Small Footprint and Low Height Packages ■ Supports Standard 5.0V as well as Low

Contextual Info: 80960RP 1.0 1.2 ABOUT THIS DOCUMENT Terminology In this document, the following terms are used: This data sheet contains ADVANCE INFORMATION about Intel’s i960 RP processor, including a func­ tional overview, mechanical data package signal locations and simulated thermal characteristics ,

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Contextual Info: in te i 82092AA PCI TO PCMCIA/ENHANCED-IDE CONTROLLER • Provides the Ultimate Plug and Play Solution fo r High Perform ance PCI Desktop Systems — Supports Combinations of PCMCIA and Enhanced Local Bus IDE Interfaces — Contains a 32-bit PCI Local Bus

Contextual Info: [PIM2>[E U T P^E^OO in te i 80960HA/HD/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Binary Compatible with Other80960 Processors • Two Instructions/Clock Sustained Execution 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers

Contextual Info: A B W A N O B O N IP O R Q W O Q N in te i 82091AA ADVANCED INTEGRATED PERIPHERAL AIP • Single-Chip PC Compatible I/O Solution for Notebook and Desktop Platforms: — 82078 Floppy Disk Controller Core — Two 16550 Compatible UARTs — One Multi-Function Parallel Port

Contextual Info: in te i 80C186EC/80C188EC AND 80L186EC/80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS • Fully Static Operation H True CMOS Inputs and Outputs ■ Integrated Feature Set: — Low-Power, Static, Enhanced 8086 CPU Core — Two Independent DMA Supported

Contextual Info: P R is y iif iiO K iÆ in r in ie l VE28F008 8 MBIT (1 MBIT x 8 FLASH MEMORY • High-Density Symmetrically Blocked Architecture — Sixteen 64 Kbyte Blocks Very High-Performance Read — 95 ns Maximum Access Time ■ Avionics Temperature Range 40°C to + 125°C

Contextual Info: 87C196CA/87C196CB 20 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0 Automotive m High Performance CHMOS 16-Bit CPU • Full Duplex Synchronous Serial I/O Port SSIO (up to 20 MHz Operation) ■ Register-Register Architecture ■ Up to 56 Kbytes of On-Chip EPROM

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Abstract: AD30/ako 451 960
Contextual Info: A E W Â N l ! DKIIF ß}[ü iflA 70® ß !0 in te l 80960J A /JF EMBEDDED 32-BIT MICROPROCESSOR High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers

Contextual Info: intei 28F016SV 16-MBIT 1 MBIT x 16, 2 MBIT x 8 FlashFileTM MEMORY Sm artVoltage Technology — User-Selectable 3.3V or 5V V cc -U s e r-S e le c ta b le 5V or 12V Vpp 65 ns Access Time 1 Million Erase Cycles per Block 30.8 M B /sec Burst W rite Transfer Rate

Contextual Info: 8x930HjrUNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER 1.0 ABOUT THIS DOCUMENT 1.2 This data sheet contains advance information about Intel’s 8*930Hjr Universal Serial Bus hub peripheral controller, based on the MCS 251 peripheral controller, which includes a functional overview,

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Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining

Contextual Info: PRODUCT PREVIEW BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT 28F004S3, 28F008S3, 28F016S3 Includes Commercial and Extended Temperature Specifications • SmartVoltage Technology — Smart 3 Flash: 2.7V Read-Only or 3.3V Vcc and 3.3V or 12V VPP

Contextual Info: intJ. 87C196KC 16-BIT HIGH-PERFORMANCE CHMOS MICROCONTROLLER Automotive • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ —40°C to + 125°C 16 Kbytes of On-Chip EPROM 232 Byte Register File 256 Bytes of Additional RAM Reglster-to-Register Architecture

Contextual Info: A O m r c i ! O M F O K fifflÄ T T O O K I in te l A28F200BR-T/B 2-MBIT 128K x 1 6 ,256K x 8 SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY Automotive Intel SmartVoltage Technology — 5V or 12V Program/Erase — 5V Read Operation Very High Performance Read

Contextual Info: in tj. 28F400BX-T/B, 28F004BX-T/B 4 MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY • x8/x16 Input/Output Architecture — 28F400BX-T, 28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ Very High-Performance Read

Contextual Info: P fö H y K ä M Ä G W in te i 80L960JA/JF 3.3V EMBEDDED 32-BIT MICROPROCESSOR 3.3 V Version o f the 80960JA/JF Processor Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model

Contextual Info: P R lO B M A IifR r ¡ n ie l M28F020 2048K 256K x 8 CMOS FLASH MEMORY Flash Electrical Chip-Erase — 5 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 /as Typical Byte-Program — 4 Second Typical Chip-Program 10,000 Erase/Program Cycles Minimum

Contextual Info: in te i 0 M F [ i3 [m Y 0 N 80960CF-33, -25,-16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • S o c k e t and O b jec t C o d e C o m p atib le w ith 8 0 96 0C A • T w o In s tru c tio n s /C lo c k S u stain ed E xecu tion • F ou r 59 M b y te s /s D M A C h an n els w ith D ata Chaining