40ETP Search Results

40ETP Price and Stock

Filter by Manufacturer

FAG Bearings


FAG Bearings B7040-E-T-P4S-UL SPINDLE BEARING, OPEN, 200MM ID, 310MM OD, 51MM WIDTH
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
RS	B7040-E-T-P4S-UL	Bulk		2 Weeks	1	1 $13833.01 10 $13833.01 100 $13833.01 1000 $13833.01 10000 $13833.01	Get Quote
FAG Bearings B71940-E-T-P4S-UL SPINDLE BEARING, OPEN, 200MM ID, 280MM OD, 38MM WIDTH
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
RS	B71940-E-T-P4S-UL	Bulk		2 Weeks	1	1 $6860.88 10 $6860.88 100 $6860.88 1000 $6860.88 10000 $6860.88	Get Quote
FAG Bearings B71940-E-T-P4S-UM SPINDLE BEARING, OPEN, 200MM ID, 280MM OD, 38MM WIDTH
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
RS	B71940-E-T-P4S-UM	Bulk		2 Weeks	1	1 $5856.82 10 $5856.82 100 $5856.82 1000 $5856.82 10000 $5856.82	Get Quote
FAG Bearings B71940-E-T-P4S-DUL SPINDLE BEARING, OPEN, 200MM ID, 280MM OD, 76MM WIDTH
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
RS	B71940-E-T-P4S-DUL	Bulk		2 Weeks	1	1 $13721.78 10 $13721.78 100 $13721.78 1000 $13721.78 10000 $13721.78	Get Quote
FAG Bearings B71940-E-T-P4S-QUL SPINDLE BEARING, OPEN, 200MM ID, 280MM OD, 152MM WIDTH
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
RS	B71940-E-T-P4S-QUL	Bulk		2 Weeks	1	1 $23427.33 10 $23427.33 100 $23427.33 1000 $23427.33 10000 $23427.33	Get Quote

Find more 40ETP price and stock on Findchips.com

40ETP Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
P3S12D40ETP Contextual Info: 512Mb DDR Synchronous DRAM P3S12D30/40ETP DESCRIPTION P3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit, 40ETP is a 4-bank x 8,388,608-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output	Original	512mb p3s12d30/40etp p3s12d30etp 216-word +4p3s12d40etp 608-word 16-bit 200mhz	PDF
IS46R16160B Abstract: zentel is43r16160b Contextual Info: IS43R83200B, IS46R83200B IS43R16160B, IS46R16160B 32Mx8, 16Mx16 256Mb DDR Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/	Original	is43r83200b is46r83200b is43r16160b is46r16160b +632mx8 16mx16 256mb conx16 66-pin zentel	PDF
Contextual Info: IS43R16160 32Mx8, 16Mx16 256Mb Synchronous DRAM PRELIMINARY INFORMATION OCTOBER 2008 FEATURES: DESCRIPTION: •฀ VDD =VDDQ = 2.5V+0.2V -5, -6, -75 •฀ Double data rate architecture ; two data transfers per clock cycle. •฀ Bidirectional , data strobe (DQS) is transmitted/	Original	is43r16160 32mx8 16mx16 256mb	PDF
IS43R83200B Abstract: 78S18 A3S56D30 IC43R16160B Contextual Info: IS43R83200B IS43R16160B, IC43R16160B 32Mx8, 16Mx16 256Mb DDR Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data	Original	is43r83200b is43r16160b ic43r16160b 32mx8 +416mx16 256mb 78s18 a3s56d30	PDF
is43r16160b-6tli Abstract: is43r16160b Contextual Info: IS43R83200B IS43R16160B, IC43R16160B 32Mx8, 16Mx16 256Mb Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -5, -6, -75 • Double data rate architecture ; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data	Original	is43r83200b is43r16160b ic43r16160b 32mx8 +616mx16 256mb 608-word is/ic43r16160b 304-word is43r16160b-6tli	PDF
Contextual Info: IS43R16800CC 8Mx16 128Mb DDR Synchronous DRAM JUNE 2009 FEATURES: DESCRIPTION: •฀ VDD =VDDQ = 2.5V+0.2V -5, -6, -75 •฀ Double data rate architecture; two data transfers per clock cycle. •฀ Bidirectional , data strobe (DQS) is transmitted/ received with data	Original	is43r16800cc 8mx16 128mb is43r16800cc-6tl +366-pin is43r16800cc-5tli is43r16800cc-6tli	PDF
IS43R16800CC Abstract: 43R16800CC A3S56D zentel ddr sdram 128Mbit 8Mx16 40ETP Contextual Info: IS43R16800CC 8Mx16 128Mb DDR Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)	Original	is43r16800cc 8mx16 128mb is43r16800cc-6tl +866-pin is43r16800cc-5tli is43r16800cc-6tli 43r16800cc a3s56d zentel ddr sdram 128mbit 8mx16 40etp	PDF
zentel Abstract: a3s56d30 IS43R16160B-6TL Contextual Info: IS43R83200B IS43R16160B PRELIMINARY INFORMATION JUNE 2007 FEATURES: DESCRIPTION: -Vdd=Vddq=2.5V+0.2V -6, -75 -Vdd=Vddq=2.6V+0.1V (-5) -Double data rate architecture ; two data transfers per clock cycle. -Bidirectional , data strobe(DQS) is transmitted/received	Original	is43r83200b is43r16160b zentel a3s56d30 +1is43r16160b-6tl	PDF
IS43R83200B Abstract: IS43R16160B zentel IS46R16160B IS43R16160B-5TL Contextual Info: IS43R83200B, IS46R83200B IS43R16160B, IS46R16160B 32Mx8, 16Mx16 256Mb DDR Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/	Original	is43r83200b is46r83200b is43r16160b is46r16160b +832mx8 16mx16 256mb is46r16160b-6tla1 is46r16160b-6bla1 is46r83200b-6tla1 zentel is43r16160b-5tl	PDF
Contextual Info: IS43R83200B, IS46R83200B IS43R16160B, IS46R16160B 32Mx8, 16Mx16 256Mb DDR Synchronous DRAM AUGUST 2010 FEATURES: DESCRIPTION: •฀ VDD =VDDQ = 2.5V+0.2V -5, -6, -75 •฀ Double data rate architecture; two data transfers per clock cycle. •฀ Bidirectional , data strobe (DQS) is transmitted/	Original	is43r83200b is46r83200b is43r16160b is46r16160b +632mx8 16mx16 256mb is46r16160b-6tla1 is46r16160b-6bla1 is46r83200b-6tla1	PDF
IS46R83200B Abstract: tsop 66 Contextual Info: IS46R83200B IS46R16160B 32Mx8, 16Mx16 256Mb Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -6, -75 • Double data rate architecture ; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)	Original	is46r83200b is46r16160b 32mx8 16mx16 +2256mb tsop 66	PDF
IS43R16160 Abstract: 43R16160 A3S56D A3S56 zentel a3s56d30 PRE-A10 Contextual Info: IS43R16160 32Mx8, 16Mx16 256Mb Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -5, -6, -75 • Double data rate architecture ; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)	Original	is43r16160 32mx8 16mx16 256mb +643r16160 a3s56d a3s56 zentel a3s56d30 pre-a10	PDF
tsop-ii 66 PIN Abstract: zentel a3s56d30 Contextual Info: IS43R83200B IS43R16160B PRELIMINARY INFORMATION APRIL 2007 FEATURES: DESCRIPTION: -Vdd=Vddq=2.5V+0.2V -6, -75 -Vdd=Vddq=2.6V+0.1V (-5) -Double data rate architecture ; two data transfers per clock cycle. -Bidirectional , data strobe(DQS) is transmitted/received	Original	is43r83200b is43r16160b tsop-ii 66 pin zentel +1a3s56d30	PDF
TSOP 66 pin Contextual Info: IS43R83200B IS43R16160B, IC43R16160B 32Mx8, 16Mx16 256Mb DDR Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data	Original	is43r83200b is43r16160b ic43r16160b 32mx8 +316mx16 256mb tsop 66 pin	PDF

Contextual Info: IS43R16800CC 8Mx16 128Mb DDR Synchronous DRAM FEATURES: • Vdd =Vddq = 2.5V+0.2V -5, -6, -75 • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK)	Original	is43r16800cc 8mx16 128mb 66-pin +3is43r16800cc-5tli is43r16800cc-6tli is43r16800cc-75tli	PDF