20G10 Search Results

a15hc

Abstract: 3959 8-pin
Contextual Info: PLD C 20G10B/PLD C 20G10 CYPRESS SEMICONDUCTOR CMOS Generic 24 Pin Reprogrammable Logic Device Features Functional Description • Fast — Commercial: tpo t X> = 10 ns, ts — Military: tp o = tc o = 15 ns, ts = = 20 = Generic architecture to replace standard logic functions

Contextual Info: PLD C 20G10B/PLD C 20G10 ìS r ’v p p u q c f SEMICONDUCTOR CMOS Generic 24 Pin Reprogrammable Logic Device Features Functional Description • Fast — Commercial: tpo t c o = 1 ns, ts — Military: tpo = t c o = 15 ns, ts = = 20 = Cypress P L D devices are high speed

20G10-18

Abstract: 12L10 16L6 18L4 20G10 20L10 20L8 PLDC20G10
Contextual Info: 20G10: 10/9/91 Revision: Wednesday, December 29, 1993 20G10B/20G10 Features D D D D D Fast Ċ Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns Ċ Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns Low power Ċ ICC max.: 70 mA, commercial Ċ ICC max.: 100 mA, military

Contextual Info: PLD C 20G10B/PLD C 20G10 CYPRESS SEMICONDUCTOR CMOS Generic 24 Pin Reprogrammable Logic Device Features Functional Description • Fast — Commercial: tpD t c o = 10 ns, ts — Military: tpD = t c o = 15 ns, ts = = 20 = Generic architecture to replace standard logic functions

12L10

Abstract: 16L6 20L10 20L8 PLD20G10C 12DC
Contextual Info: 4bE SEMICONDUCTOR SSÔTbtS D OGGbTMM PRELIMINARY CYPRESS SEMICONDUCTOR Features • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpD = 7.5 ns — tsu = 3 ns — fM A X = 1 0 5 M tte • Reduced ground bounce and under­

Contextual Info: 7 20G10C C YPRESS • Features • Ultra high speed supports today’s and tomorrow’s fastest microprocessors Generic 24-Pin PAL Device 10 user-programmable output macrocells — Output polarity control — Registered or combinatorial operation — tpo = 7.5 ns

Contextual Info: 20G10B/20G10 CYPRESS Features • Fast — Commercial: tpp - 15 ns, tc o — 10 ns, tg = 12 ns — Military: tpp = 20 ns, tc o = 15 ns, tg = 15 ns CMOS Generic 24-Pin Reprogrammable Logic Device • Generic architecture to replace stan­ dard logic functions including: 20L10,

256K x 8 SRAM CY7C128A SRAM

Abstract: 5962-86705 PLD28 5962-89935 pld20ra10 5962-89598 CY7C132 cy7c291 PLD20RA PLDC20G10
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number Speed (ns) ICC/ISB/ICCDR (mA @ ns) 883 Availability 1K 256 x 4 22 CY7C122 5962-88594 tAA = 25, 35 90 @ 25 Now 4K 1K x 4—Separate I/O 24S CY7C150 5962-88588 tAA = 25

20G10-25

Abstract: 20G10-30 20G10B-20 20G10B-25 12L10 16L6 18L4 20L10 20L8 20G108
Contextual Info: 20G10B/20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable — Uses proven EPROM technology • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns — Fully AC and DC tested

Contextual Info: y 20G10B/20G10 CYPRESS Features • Fast — Commercial: tpo = 15 ns, tco — 10 ns, ts = 12 ns — Military: tpo = 20 ns, tco = 15 ns, ts = 15 ns • Low power — Ice max.: 70 mA, commercial — Ice max.: 100 mA, military • Commercial and military temperature

12L10

Abstract: 16L6 20L10 20L8 PLDC20G10 PLDC20G10B ULTRA37000
Contextual Info: 20G10B 20G10 USE ULTRA37000 FOR ALL NEW DESIGNS CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns — Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns

20G10

Abstract: 20G10B-20 12L10 16L6 18L4 20L10 20L8
Contextual Info: fax id: 6014 1P LDC20 G1 0B/P LD C20 G1 0 20G10B/20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable — Uses proven EPROM technology • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns

7C245

Abstract: b1225 CERAMIC QUAD FLATPACK CQFP 22V10 PAL CMOS device 228X 16R8 7B991 PAL20 7C404 7C128
Contextual Info: Ordering Information RAM, PROM, Dual-Port Static RAM, FIFO, Data Communications PREFIX DEVICE CY CY CY CY CY CY 7C128 62256 7C245 7C006 7C404 7B991 C = CMOS B = BiCMOS SUFFIX -45 D L-70 S L-35 P V-15 J -25 D -5 J MB C C C MB C FAMILY CMOS SRAM - FAST CMOS SRAM - SLOW

IAEJE

Abstract: PLDC20G10C R123A HC-49/IAEJE IC 2 5/IAEJE
Contextual Info: 20G10B/20G10 P Y P P C ’C O CMOS Generic 24-Pin Reprogrammable Logic Device Features • Fast — Commercial: tpo = IS ns, to o = 10 ns, ts - 12 ns — Military: tpo = 20 ns, tc o = 15 ns, tg = IS ns • Low power — Ic c max.: 70 mA, commercial

CERAMIC QUAD FLATPACK CQFP

Abstract: 64 CERAMIC LEADLESS CHIP CARRIER LCC CERAMIC LEADLESS CHIP CARRIER PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC CY74FCT CERAMIC LEADLESS CHIP CARRIER LCC 24 ic 62256 dual flatpack 8 PAL20 22V10 PAL CMOS device
Contextual Info: Ordering Information RAM, PROM, Dual-Port Static RAM, FIFO, Data Communications PREFIX DEVICE CY CY CY CY CY CY 7C128 62256 7C245 7C006 7C404 7B991 C = CMOS B = BiCMOS SUFFIX -45 D L-70 S L-35 P V-15 J -25 D -5 J MB C C C MB C FAMILY CMOS SRAM - FAST CMOS SRAM - SLOW

state-machine structure

Abstract: PDF IC 9012 SR flip flop using discrete gates 123B 20G10 CY7C277 PALCE22V10 PLDC20G10 S12A S12B
Contextual Info: fax id: 6423 State Machine Design Considerations and Methodologies The use of state machines provides a systematic way to design complex sequential logic circuits—an increasingly popular approach since the advent of PLD Programmable Logic Device circuitry. This application note describes the many

Contextual Info: 20G10C ¡5 r CYPRESS SEMICONDUCTOR Features • • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpD = 7.5 ns Generic 24-Pin PAL Device 10 user-programmable output macrocells — Output polarity control U sing B iC M O S process and Ti-W fuses,

lmw14

Contextual Info: 20G10B/PLDC20Gt0 i f C Y PR ESS CMOS Generic 24-Pin Reprogrammable Logic Device F ea tu res • Fast — C om m ercial: Ip» = 15 n s, t o = 10 n s, l s = 12 ns — M ilitary: tpu = 20 n s, t( <> = *5 n s, ts = 15 ns • G eneric arch itectu re to replace sta n ­

16v8

Abstract: 18V8 EEL22 EP330 16P2 16R4 22p10 TM 1618 16r8 "EEL-22"
Contextual Info: 6. T a b le o f C o m p a t ib ilit y w it h PLD s b y O th e r M a k e rs T o replace P L D s from other m a k e rs w ith T o sh ib a P L D s, refer to the follow ing tab le. The tab le lists P L D s which are lo gically com patible, in clu d in g e xtern al pin specification s, with

12L10

Abstract: 16L6 18L4 20L10 20L8
Contextual Info: 20G10C i f CYPR ESS Features • 10 user-programmable output macrocells — Output polarity control — Registered or combinatorial operation — Pin or product term output enable control • Ultra high speed supports today’s and tomorrow’s fastest microprocessors

qml-38535

Abstract: 5962-8863702LA 20G10 marking YJ AM smd code Yj 33 PLD-30
Contextual Info: OREVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED Changes in accordance with NOR 5962-R005-91 91 - 0 9 - 2 4 Michael A. Frve Changed the minimum clock period for device 02 from 45 to 40 ns. Boilerplate update, ksr_ 99 - 07 - 28

20G10

Abstract: S12B 123B CY7C277 PALCE22V10 PLDC20G10 S12A bit-slice PALC20G10
Contextual Info: State Machine Design Considerations and Methodologies The use of state machines provides a systematic way to design complex sequential logic circuits—an increasingly popular approach since the advent of PLD Programmable Logic Device circuitry. This application note describes the many

Contextual Info: 20G10B/20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Generic architecture to replace stan­ dard logic functions including: 20L10, 20L8,20R8,20R6,20R4,12L10,14L8, 16L6,18L4,20L2, and 20V8 Eight product term s and one OE product term per output

22V10-Macrocell

Abstract: 99522 PLD20RA10 22V10D 5962-89598 cy7c291 CY7C425 PALC22V10B CY6116A CY7C128A
Contextual Info: Military Product Selector Guide Static RAMs Size Organization Pins DIP SMD Number Part Number 16K 2K x 8—CS Power-Down 24S CY7C128A 16K 2K x 8—CS Power-Down 24 CY6116A 64K 8K x 8—CS Power-Down 28S CY7C185A 256K 32K x 8—CS Power-Down 28 CY7C198 256K