200PF Search Results

VC06LC18X500

Abstract: VC04LC18V500 VC08LC18A500
Contextual Info: StaticGuard AVX Multilayer Ceramic Transient Voltage Suppressors ESD Protection for CMOS, Bi Polar and SiGe Based Systems GENERAL INFORMATION • Typical ESD failure voltage for CMOS and/or Bi Polar is ≥ 200V. • Low capacitance <200pF is required for high-speed

Contextual Info: IDT54/74FCT163652/A/C PRODUCT PREVIEW 3.3V CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS Integrated Device Technology, Inc. FEATURES: • 0.5 MICRON CMOS Technology • Typical tsK o (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: 3.3V CMOS SINGLE INVERTER GATE DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 0.65mm pitch PSOP package Extended commercial range o f - 4 0 ° C to + 8 5 °C Vcc = 3.3V ± 0.3V, Normal Range

Contextual Info: 3.3V CMOS 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD D E S C R IP TIO N : FE A T U R E S : - 0.5 MICRON CMOS Technology Typical tSK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: 3.3V CMOS SINGLE INVERTER GATE WITH 5 VOLT TOLERANT I/O J m ï ï ., D E S C R IP TIO N : FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 0.65mm pitch PSOP package Extended commercial range of - 40°C to +85°C

Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O IDT74LVC16500A ADVANCE INFORMATION DESCRIPTION: FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: IDT74FCT3244/A 3.3V CMOS OCTAL BUFFER/LINE DRIVER H htegiated D e v iz e T e c h n o lo g y , l i e . FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 • Extended commercial range of -40°C to +85°C

Contextual Info: 3.3V CMOS HEX INVERTER WITH OPEN-DRAIN OUT­ PUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - IDT74LVC05A ADVANCE INFORMATION 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP and

Contextual Info: 3.3V CMOS OCTAL BUFFER/DRIVER WITH 3STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD FE A T U R E S : - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.65mm pitch SSOP,

Contextual Info: 3.3 V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS BE FEATURES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 0.635mm pitch SSOP, 0.50mm pitch TSSOP,

Contextual Info: 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.635mm pitch QSOP,

Contextual Info: 3.3V CMOS HEX INVERTER WITH 5 VOLTTOLERANT I/O FEATURES: - DESCRIPTION: 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages

Contextual Info: 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NAND GATE, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages

Contextual Info: 3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD BE FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages

Contextual Info: 3.3V CMOS 16-BIT BUFFER/ DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP

Contextual Info: 3.3V CMOS 18-BIT UNIVERSAL BUSTRANSCEIVER WITH 3-STATE OUTPUTS AND BUS HOLD DESCRIPTION: FEATURES: - 0.5 M ICRO N C M O S Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per M IL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: IDT74LVCU04A ADVANCE INFORMATION 3.3V CMOS HEX INVERTER WITH 5 VOLT TOLERANT I/O FE A T U R E S : - 0.5 MICRON CMOS Technology - ESD > 2000V per MlL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.65mm pitch SSOP and

Contextual Info: 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE WITH 5 VOLT TOLERANT I/O FE A T U R E S : - IDT74LVC1G86A ADVANCE INFORMATION D E S C R IP TIO N : - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0

Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - Typical tS K o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: 3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD DESCRIPTION: FEATURES: - IDT74ALVCH32373 ADVANCE INFORMATION 0.5 M ICRO N C M O S Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per M IL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: 3.3V CMOS 18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD FE A T U R E S : - 0.5 MICRON CMOS Technology - Typical - tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 0.635mm pitch S SO P , 0.50mm pitch T SSO P,

Contextual Info: _ irr R i D E S C R IP T IO N : FEATURES: This quadruple 2-input positive-AND gate is built using advanced - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; - > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch S S O P and

Contextual Info: 3.3V CMOS 1-BITTO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD DESCRIPTION: FEATURES: - IDT74ALVCH16344 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER, WITH ADDRESS LATCHES FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.635mm pitch QSOP, 0.65mm pitch SSOP, 0.65mm pitch TSSOP packages