IDT74L Search Results

LVCH16541A

Abstract: IDT74LVCH16541A
Contextual Info: IDT74LVCH16541A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUFFER/ DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION FEATURES: – – – – – – – – – IDT74LVCH16541A

LVCH16540A

Abstract: LVCH16540
Contextual Info: IDT74LVCH16540A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVCH16540A 3.3V CMOS16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: – – – – – – –

IDT74LVCH16701A

Abstract: LVCH16701A SO56-2 701A
Contextual Info: IDT74LVCH16701A 3.3V CMOS 18-BIT READ/WRITE BUFFER, 5 VOLT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT READ/WRITE BUFFER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: IDT74LVCH16701A DESCRIPTION: – – Typical tSK 0 (Output Skew) < 250ps

LVCH373A

Contextual Info: IDT74LVCH373A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: – – – – – – – – – – IDT74LVCH373A

Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O IDT74LVC16500A ADVANCE INFORMATION DESCRIPTION: FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: 3.3V CMOS HEX INVERTER WITH OPEN-DRAIN OUT­ PUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - IDT74LVC05A ADVANCE INFORMATION 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP and

Contextual Info: IDT74LVC139A 3.3V CMOS DUAL ADVANCE INFORMATION 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 M IC R O N C M O S T e c h n o lo g y E SD > 2 0 0 0 V p e r M IL -S T D -8 8 3 , M e th o d 3 0 1 5 ; > 2 0 0 V using m a c h in e m o d e l C = 2 0 0 p F , R = 0

Contextual Info: 3.3 V CMOS 18-BIT REGISTER 3-STATE , 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - IDT74LVC16823A ADVANCE INFORMATION The LVC16823A18-bit edge-triggered D-type register is built using advanced dual metal CMOS technology.This high-speed, low-power register is ideal for use as a buffer register for data

Contextual Info: IDT74LVCH16240A 3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: - designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can

Contextual Info: 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; IDT74LVC823A ADVANCE INFORMATION D E S C R IP TIO N : The LVC823A 9-bit bus-interface flip-flop is built using advanced dual

Contextual Info: IDT74LVCU04A ADVANCE INFORMATION 3.3V CMOS HEX INVERTER WITH 5 VOLT TOLERANT I/O FE A T U R E S : - 0.5 MICRON CMOS Technology - ESD > 2000V per MlL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.65mm pitch SSOP and

Contextual Info: 3.3V CMOS SINGLE 2-INPUT EXCLUSIVE-OR GATE WITH 5 VOLT TOLERANT I/O FE A T U R E S : - IDT74LVC1G86A ADVANCE INFORMATION D E S C R IP TIO N : - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0

Contextual Info: IDT74LVC16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: The LVC16601A 18-bit universal bus transceiver is built using advanced dual metal C M O S technology.This 18-bit uni­ versal bus transceiver combines D-type latches and D-type

Contextual Info: IDT74LVCH32373A 3.3V CMOS 32-BIT ADVANCE TRANSPARENT D-TYPE LATCH INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD DESCRIPTION: FEATURES: - Typical tS K o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: IDT74LVC623A 3.3V CMOS OCTAL ADVANCE INFORMATION TRANSCEIVER WITH DUAL ENABLE, 3-STATE OUT­ PUTS, 5 VOLT TOLERANT I/O FEATURES: - 0.5 M IC R O N C M O S Technology E S D > 2 0 0 0 V per M IL -S T D -8 8 3 , Method 3 0 15; > 2 0 0 V using m achine model C = 2 0 0 p F , R = 0

Contextual Info: 3.3V CMOS 16-BIT IDT74L VCH16952A REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD D E S C R IP TIO N FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: 3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER WITH BUS HOLD, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - IDT74LVCH16344A ADVANCE INFORMATION The LVCH16344A is a 1 :4 address line driver built using advanced dual metal C M O S technology. This high speed, low power device provides the ability to fanout to memory

Contextual Info: 3.3V CMOS OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5V TOLERANT I/O DESCRIPTION: FEATURES: - IDT74LVC543A ADVANCE INFORMATION 0.5 M IC RO N C M O S Technology ESD > 2000V per M IL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0

Contextual Info: IDT74LVC137A 3.3V CMOS ADVANCE INFORMATION 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER, WITH ADDRESS LATCHES is designed for high-performance memory-decoding or datarouting applications requiring very short propagation delay times. In high-performance memory systems, this decoder mini­

Contextual Info: 3.3V CMOS SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT AND 5 VOLT TOLERANT I/O J m ïï. , D E S C R IP TIO N : FE A T U R E S : - IDT74LVC1G126A ADVANCE INFORMATION - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0

Contextual Info: IDT74LVCH162543A 3.3V CMOS 16-BIT ADVANCE REGISTERED TRANSCEIVER INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD flow. The A-to-B enable CEAB must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent lowto-high transition of LEAB puts the A latches in the storage

Contextual Info: 3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP

Contextual Info: IDT74LVC1G79A 3.3V CMOS ADVANCE INFORMATION SINGLE POSITIVE-EDGETRIGGERED D-TYPE FLIPFLOP, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - This single positive-edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. The LVC1G79A is designed for 2.3V to 3.6V V cc operation.

Contextual Info: IDT74LVC1G125A 3.3V CMOS ADVANCE INFORMATION SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - The LVC1G125A single bus buffer gate is built using ad­ vanced dual metal CMOS technology. The LVC1G125A is de­ signed for 1,65V to 3.6V V cc operation and features indepen­