1DD13 Search Results

Contextual Info: * ULTRA-HIGH-SPEED 64-WORD x 18-BIT FIFO SYNERGY SY69168 SEMICONDUCTOR FEATURES DESCRIPTION • 10ns read and/or write cycle ■ System clock speeds to 100MHz ■ Selectable OVERFLOW and UNDERFLOW interrupts ■ EMPTY, FULL and HALF-FULL status flag outputs

SY89429ZC

Contextual Info: * FR EQ U EN C Y S Y N TH ES IZER SYNERGY Clockworks PRELIMINARY SY89429 SEMICONDUCTOR DESCRIPTION FEATURES • 25 to 400MHz differential PECL outputs ■ ±25ps output jitter within 100 cycles ■ Minimal frequency over-shoot ■ Synthesized architecture

123 DAL

Abstract: synergy series SY100H602 SY10H602 SY10H602JC q213
Contextual Info: * 9-BIT LATCHED TTL-TO-ECL SYNERGY S E M IC O N D U C T O R FEATURES DESCRIPTION I 9-bit ideal for byte-parity applications T he SY 10/100H 602 are 9-bit, dual supply TTL-to-E C L tran sla to rs w ith latches. D evices in the S ynergy 9-bit tra n sla to r series utilize the 28-lead PLCC fo r optim al

Contextual Info: ^ 4-STAGE COUNTER/ SHIFTREGISTER SYNERGY SY100S336 SEMICONDUCTOR FEATURES DESCRIPTION • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 110Ops ■ Iee min. o f-1 7 0 m A ■ ESD protection of 2000V ■ Internal 75K Q input pull-down resistors

Contextual Info: « SY10EL01 SY100EL01 4-INPUT OR/NOR SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • 2 3 0 p s p ro p a g a tio n d e lay The SY10/100EL01 are 4-input OR/NOR gates. These devices are functionally equivalent to the E101 devices, with higher performance capabilities. With propagation

Contextual Info: * SY10494-6/7 SY100494-6/7 SY101494-6/7 16K x 4 ECL RAM SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • Address access time, tAA: 6/7ns max. The Synergy S Y 1 0 /1 0 0 /1 0 1 4 9 4 are 65536-bit Random Access Memories RA M s , designed with advanced Emitter

Contextual Info: « SYNERGY SEMICONDUCTOR S IN G L E S U P P L Y P E C L -T T L ClockW orks1M 1 : 4 C L O C K D R IV E R SvTo/lo'oHsla DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-TTL ■ 300ps pin-to-pin skew ■ Guaranteed skew spec ■ Differential internal design for increased noise

Contextual Info: * SYNERGY SONET/SDH/ATM QUAD OC-3 CLOCK RECOVERING TRANSCEIVER S mS SEMICONDUCTOR FEATURES DESCRIPTION • A complete single-chip 4 Channel Transmitter & Receiver ■ Complies with Bellcore, ITU/CCITT and ANSI specifications ■ Compatible with VLSI VNS67200 SUNI and IgT WAC413-A ATM Quad-UNI Processor

Contextual Info: *SYNERGY SY10EL51 SY100EL51 DIFFERENTIAL CLOCK D FLIP-FLOP SEMICONDUCTOR DESCRIPTION FEATURES • 475ps propagation delay T he SY10/100EL51 are differential clock D flip -flop s with reset. T hese devices are fun ction a lly sim ila r to the E151 devices, with higher perform ance capabilities. With

F100K

Abstract: SY100S336 SY100S336A SY100S336ADC
Contextual Info: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER m v SYNERGY . Vim <N «4 S i i 00S336A S E M IC O N D U C T O R DESCRIPTION FEATURES • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 110Ops ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50%

HX8357-D01

Abstract: MIPI dbi data rate hx8357
Contextual Info: DATA SHEET DOC No. HX8357-D00/D01-DS HX8357-D00/D01 320RGB x 480 dot, 16M color, with internal GRAM, TFT Mobile Single Chip Driver Temporary Version 00 April, 2012 HX8357-D00/D01 320RGB x 480 dot, 16M color, with internal GRAM, TFT Mobile Single Chip Driver

Contextual Info: [O rd e rin g n u m b e r :EN 5761 C M O S IC LC74201JE I S A fÊ Ÿ O l Single Chip MPEG Decoder Overview Package Dimensions T h e L C 7 4 2 0 1 JE is a C M O S IC that in teg rates the signal unit: m m p ro cessin g fu n ctio n s req u ired o f a v id eo C D d eco d er to a

Contextual Info: * 6-BIT UNIVERSAL UP/DOWN COUNTER SYNERGY SY10E136 SY100E136 SEMICONDUCTOR DESCRIPTION FEATURES 550MHz count frequency Extended 100E V ee range of -4.2V to -5.5V Look-ahead-carry input and output Fully synchronous up and down counting Asynchronous Master Reset

F100K

Abstract: SY100S336 SY100S336A SY100S336ADC PN800
Contextual Info: 4-STAGE COUNTER/ SHIFT REGISTER SYNERGY S EM IC O N D U C TO R FEATURES I l I l l I SY100S336A D E S C R IP T IO N Max. shift frequency of 700MHz Clock to Q delay max. of HOOps Sn to TC speed Improved by 50% Sn set-up and hold time reduced by more than 50%