TDD13FLL Search Results

850C

Abstract: F100K SY100S364
Contextual Info: <& SY100S364 16-INPUT MULTIPLEXER SYNERGY S EM IC O N D U C TO R FEATURES • ■ Max. propagation delay of 1300ps min. of -63mA ■ ESD protection of 2000V ■ Ie e ■ Industry standard 100K ECL levels ■ Extended supply voltage option: V ee = -4.2V to -5.5V

SY89429ZC

Contextual Info: * FR EQ U EN C Y S Y N TH ES IZER SYNERGY Clockworks PRELIMINARY SY89429 SEMICONDUCTOR DESCRIPTION FEATURES • 25 to 400MHz differential PECL outputs ■ ±25ps output jitter within 100 cycles ■ Minimal frequency over-shoot ■ Synthesized architecture

SY100E336

Abstract: SY10E336
Contextual Info: * 3-BIT REGISTERED BUS TRANSCEIVER SYNERGY S E M IC O N D U C T O R FEATURES SY10E336 SY100E336 DESCRIPTION I 25Q cutoff bus output I Extended 100E V ee range of -4 .2 V to -5 .5 V I 5012 receiver output I Transm it and receive registers I 1500ps max. clock to bus

Contextual Info: « QUINT 2-INPUT OR/NOR GATE SYNERGY SY100S302 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 700ps T h e S Y 1 0 0 S 3 0 2 o ffe rs fiv e 2 -in p u t O R /N O R g a te s d e s ig n e d fo r u se in h ig h -p e rfo rm a n c e E C L s y s te m s . T h e

synergy acr

Abstract: E166 SY100E166 SY100E166JC SY10E166 SY10E166JC EZ-214
Contextual Info: * 9-BIT MAGNITUDE COMPARATOR SYNERGY S E M IC O N D U C TO R FEATURES D E S C R IP T IO N • 11 OOps max. Propagation Delay A = B ■ ESD protection of 2000V ■ Fully compatible with industry standard 10KH, 100K ECL levels ■ Extended 100E V e e range of -4.2V to -5.46V

Contextual Info: * SYNERGY ULTRA-HIGH-SPEED 64-WORD x 18-BIT FIFO SEMICONDUCTOR PRELIMINARY SY69167 SY69267 DESCRIPTION FEATURES • System clock speeds to 200MHz ■ User-selectable bandwidth — one read or one write operation each clock cycle ■ Selectable O VERFLOW and UNDERFLOW Interrupts