Y100S Search Results

ic 3525 internal block diagram

Abstract: s815
Contextual Info: * SINGLE SUPPLY QUAD SYNERGY C lockworks Y100S815 PECL/TTL-TO-PECL SEMICONDUCTOR FEATURES • ■ Quad PECL version of popular ECLinPS El 11 ■ Low skew ■ Guaranteed skew spec ■ TTL enable Input ■ Selectable TTL or PECL clock input ■ Single +5V supply

F100K

Abstract: SY100S325
Contextual Info: * _ _ LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY Y100S325 SEMICONDUCTOR DESCRIPTION FEATURES The Y100S325 are hex translators fo r converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting o r differential receivers. An

F100K

Abstract: SY100S331 SY100S331DC
Contextual Info: * SYNERGY TRIPLE D FLIP-FLOP Y100S331 S E M IC O N D U C T O R FEATURES DESCRIPTION I Max. toggle frequency of 800MHz I Differential outputs I I e e min. of -80m A The Y100S331 offers three D-type, edge-triggered m aster/slave flip -flop s with true and com plem ent outputs,

Contextual Info: ^ 4-STAGE COUNTER/ SHIFTREGISTER SYNERGY Y100S336 SEMICONDUCTOR FEATURES DESCRIPTION • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 110Ops ■ Iee min. o f-1 7 0 m A ■ ESD protection of 2000V ■ Internal 75K Q input pull-down resistors

F100K

Abstract: SY100S304 SY100S304DC SY100S304JC
Contextual Info: * QUINT AND/NAND GATE SYNERGY SEMICONDUCTOR FEA TU RES Y100S304 D E S C R IP T IO N Max. propagation delay of I050ps Ie e min. of -60mA ESD protection of 2000V Extended supply voltage option: — VEE = -4.2V to -5.46V Voltage and temperature compensation for

F100K

Abstract: SY100S313 SY100S313DC SY100S313FC
Contextual Info: X> SYNERGY QUAD DRIVER Y100S313 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 800ps Enable to Output max. of 950ps T h e S Y 1 0 0 S 3 1 3 o ffe rs fo u r d riv e rs w ith tw o O R an d tw o N O R o u tp u ts , d e s ig n e d fo r u se in h ig h -p e rfo rm a n c e E C L

Contextual Info: * M . - 2 / 3 OR -5-2, +4/6) CLOCK GENERATION CHIP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization ■ Internal 75Ki2 input pull-down resistors ■ ESD protection of 2000V

811Z

Contextual Info: * SING LE SUPPLY 1:9 SYNERGY Clockworks Y100S811 P EC L/TTL-TO -PECL S E M IC O N D U C T O R FEATURES DESCRIPTION PECL version of popular ECLinPS El 11 Low skew Guaranteed skew spec V bb output TTL enable input Selectable TTL or PECL clock input Single +5V supply

F100K

Abstract: SY100S318 SY100S318DC
Contextual Info: * 5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE SYNERGY Y100S318 S E M IC O N D U C T O R FEATURES • ■ Max. propagation delay of 800ps ■ Iee min. of -55m A ■ ESD protection of 2000V ■ Extended supply voltage option: V ee = -4.2V to -5.5V ■ Voltage and temperature compensation for

F100K

Abstract: SY100S370 SY100S370DC
Contextual Info: * . . . UNIVERSAL DEMULTIPLEXER/DECODER SYNERGY S Y 100S 370 _ SE M IC O N D U C TO R U FEATURES • Max. propagation delay of 1200ps ■ I e e min. of -92mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: