SY10H602JCTR Search Results

Contextual Info: 9-BIT L A T C H E D SYNERGY . TTL-TO-ECL - v . MHt . . S E M IC O N D U C T O R FEATURES • 9-bit ideal for byte-parity applications ■ Fully compatible with Motorola MC10H/100H602 The SY10/100H602 are 9-bit, dual supply TTL-to-ECL translators with latches. Devices in the Synergy 9-bit

100H602

Abstract: SY100H602 SY10H602 SY10H602JC SY10H602JCTR
Contextual Info: 9-BIT LATCHED TTL-TO-ECL SY10H602 SY100H602 DESCRIPTION FEATURES • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply ■ 3.5ns max. D to Q ■ PNP TTL inputs for low loading

123 DAL

Abstract: synergy series SY100H602 SY10H602 SY10H602JC q213
Contextual Info: * 9-BIT LATCHED TTL-TO-ECL SYNERGY S E M IC O N D U C T O R FEATURES DESCRIPTION I 9-bit ideal for byte-parity applications T he SY 10/100H 602 are 9-bit, dual supply TTL-to-E C L tran sla to rs w ith latches. D evices in the S ynergy 9-bit tra n sla to r series utilize the 28-lead PLCC fo r optim al

Contextual Info: * 9-BIT LATCHED TTL-TO-ECL SYNERGY SY10H602 SY100H602 S E M IC O N D U C T O R FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply

Contextual Info: * SYNERGY 9-BIT LATCHED TTL-TO-ECL SY10H602 SY100H602 SEMICONDUCTOR FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply ■ 3.5ns max. D to Q

Contextual Info: * SYNERG Y 9-B IT LATCHED TTL-TO -EC L SY10H602 SY100H602 SEMICONDUCTOR FEATURES DESCRIPTION 9-bit ideal for byte-parity applications Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply 3.5ns max. D to Q PNP TTL inputs for low loading

Contextual Info: SY10H602 SY100H602 FINAL 9-BIT LATCHED TTL-TO-ECL DESCRIPTION FEATURES • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply ■ 3.5ns max. D to Q ■ PNP TTL inputs for low loading

SY100H602

Abstract: SY10H602 SY10H602JC SY10H602JCTR
Contextual Info: SYNERGY SY10H602 SY100H602 9-BIT LATCHED TTL-TO-ECL SEMICONDUCTOR SYNERGY SY10H602 SY100H602 SEMICONDUCTOR FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize

Contextual Info: * SYNERGY 9-BIT LATCHED TTL-TO-ECL SY10H602 SY100H602 SEMICONDUCTOR FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply ■ 3.5ns max. D to Q

Contextual Info: * 9 -B IT L A T C H E D SYNERGY T T L -T O -E C L SY10H602 SY100H602 SEMICONDUCTOR FEATURES DESCRIPTION 9-bit ideal for byte-parity applications Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply 3.5ns max. D to Q

SY100H602

Abstract: SY10H602
Contextual Info: • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ Dual supply ■ 3.5ns max. D to Q ■ PNP TTL inputs for low loading ■ Choice of ECL compatibility: MECL 10KH 10Hxxx