1750A PROCESSOR ARCHITECTURE Search Results

dsp radiation tolerance

Contextual Info: P1750AE/SOS SINGLE CHIP, 30MHz, ENHANCED SPACE PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip MIL-STD-1750AE Processor Form-Fit-Functionally Compatible with the P1750A CMOS Processor DAIS Instruction Mix Execution Performance

ADR7

Abstract: PACE1750A
Contextual Info: PACE1753/SOS SINGLE CHIP, MIL-STD-1750A MMU CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES • Implements the MIL-STD>1750A Instractlon Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory 10,240 bits for both the MMUand BPU

TDA 965

Abstract: MIL-STD-1750A 1750A processor architecture
Contextual Info: PACE1753/SOS SINGLE CHIP, MIL-STD-1750A MMU CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES • implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory 10,240 bits for both the MMU and BPU

HX1750

Abstract: mil-std-1750a 1750a 1750A processor architecture honeywell defense Honeywell 1 day timer MIL-STD-1750
Contextual Info: HX1750 MIL-STD-1750A Microprocessor The HX1750 is a true single chip implementation of the MIL-STD-1750A instruction set architecture, fabricated on Honeywell's Silicon on Insulator CMOS SOI-IV process. It combines a fast 16 bit microprocessor, a 40 bit floating point processor,

pace1750

Abstract: 1750a PACE1750AE
Contextual Info: P1750AE/SOS SINGLE CHIP, 30MHz, ENHANCED SPACE PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip MIL-STD-1750AE Processor Form-Fit-Functionally Compatible with the P1750A CMOS Processor DAIS Instruction Mix Execution Performance

edc5

Abstract: P1753 Pyramid Semiconductor pace1750 PACE1753 mil-std-1750a 5962-8950504XX IB10 5962-8950502UX RAM EDAC SEU
Contextual Info: PACE1753/SOS SINGLE CHIP, MIL-STD-1750A MEMORY MANAGEMENT UNIT MMU CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and

Contextual Info: PACE1750A SINGLE CHIP, 15MHz to 40MHz, CMOS 16-BIT PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip PACE TechnologyTM CMOS 16-Bit Processor with 32 and 48-Bit Floating Point Arithmetic DAIS Instruction Mix Execution Performance

P1750A

Abstract: P1750A-15CMB 5962-8766503YX pace1750a P1750A-15GMB MIL-STD-1750 P1750A-20PGMB 5962-8766501TX P1750A-30QGMB IB14
Contextual Info: PACE1750A SINGLE CHIP, 15MHz to 40MHz, CMOS 16-BIT PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip PACE TechnologyTM CMOS 16-Bit Processor with 32 and 48-Bit Floating Point Arithmetic DAIS Instruction Mix Execution Performance

as3 SMD Transistor

Abstract: IB435 AK010 mil-std-1750 PACE1750A PACE1750AE P1750A mil-std-1750a smd ak3
Contextual Info: PACE1750AE SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip PACE TechnologyTM CMOS 16-Bit Processor with 32 and 48-Bit Floating Point Arithmetic Form-Fit-Functionally Compatible with the

1750A processor architecture

Abstract: PACE1750A KTC AS1-708N
Contextual Info: PACE1750AE SINGLE CHIP, 40MHz, ENHANCED CMOS 16-BIT PROCESSOR 4 - — FEATURES — - — • Implements the MIL-STD-1750A Instruction Set Architecture ■ Single Chip PACE Technology CMOS 16-BH Processor with 32 and 48-Bit Floating Point

Contextual Info: PACE1750AE SINGLE CHIP, 20MHz to 40MHz, ENHANCED CMOS 16-BIT PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip PACE TechnologyTM CMOS 16-Bit Processor with 32 and 48-Bit Floating Point Arithmetic Form-Fit-Functionally Compatible with the

Contextual Info: P1750A/SOS SINGLE CHIP, 20MHz to 30MHz, CMOS/SOS SPACE PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Built-In Self Test 24 User Accessible Registers CMOS/SOS Processor with 32 and 48-Bit Floating Point Arithmetic Single 5V ± 10% Power Supply

pace1750

Abstract: as3 SMD Transistor PACE1750A
Contextual Info: P1750A/SOS SINGLE CHIP, 20MHz to 30MHz, CMOS/SOS SPACE PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Built-In Self Test 24 User Accessible Registers CMOS/SOS Processor with 32 and 48-Bit Floating Point Arithmetic Single 5V ± 10% Power Supply

P1750A performance

Abstract: 5962-8766501TX P1750A20PGM P1750A-20PGMB
Contextual Info: PACE1750A SINGLE CHIP, 40MHz, CMOS 16-BIT PROCESSOR - • : — ; : FEATURES ■ Implements the MIL-STD-1750A Instruction Set Architecture ■ 20,30 and 40 MHz operation over the Military Temperature Range ■ Single Chip PACE Technology CMOS 16-Bit Processor with 32 and 48-Bit Floating Point

EDENE

Contextual Info: PACE1750A SINGLE CHIP, 40MHz, CMOS 16-BIT PROCESSOR 4 -FEATURES • Implements the MIL-STD-1750A instruction Set Architecture ■ 20,30 and 40 MHz operation over the Military Temperature Range ■ Single Chip PACE Technology CMOS 16-Blt

Contextual Info: PACE1750AE SINGLE CHIP, 40MHz, ENHANCED CMOS 16-BIT PROCESSOR FEATURES • Im plem ents th e M IL-STD-1750A Instruction Set Architecture ■ Single Chip PACE Technology CM OS 16-Bit Processor with 32 and 48-Bit Floating Point Arithm etic ■ Form-Fit-Functionally Com patible with the P1750A

1750A processor architecture

Abstract: 2 BIT ALU IC 8 BIT ALU IC 4 bit barrel shift register 4 BIT ALU IC register file "processor" "shift register" alu Barrel Shifter 16 bits 1750A processor interrupt architecture
Contextual Info: E S O L I D STATE 17E D 3ä7S0fll □ □ S S 4 0 Ö T Radiation-Hardened High-Reliability IC s . T -s z ^ o 1750A Central Processor Unit i 1750A CPU Parts List Quantity Features: • Eleven Chip Set 6- Standard Cell IC's, 3,000 Gate 5- 32 K ROM's • 100 Kilo Rads

Contextual Info: PACE1750A SINGLE CHIP, 40MHz, CMOS 16-BIT PROCESSOR FEATURES • Implements the MIL-STD-1750A Instruction Set Architecture ■ 20, 30 and 40 MHz operation over the Military Temperature Range ■ Single Chip PACE Technology CMOS 16-Blt Processor with 32 and 48-Blt Floating Point

Contextual Info: MARCH 1995 MA31750 DS3748-6.5 MA31750 HIGH PERFORMANCE MIL-STD-1750 MICROPROCESSOR The GEC Plessey MA31750 is a single-chip microprocessor that implements the full MIL-STD-1750A instruction set architecture, or Option 2 of Draft MIL-STD1750B. The processor executes all mandatory instructions and

MA31750 processor architecture

Abstract: nte 4006 MA31750 CMOS 4002 l7 723 M/A MIL-STD-1750B mil-std-1750a ttl nim a006 GNDA15
Contextual Info: MA31750 MA31750 High Performance MIL-STD-1750 Microprocessor Replaces July 1999 version, DS3748-7.0 DS3748-8.0 January 2000 The Dynex Semiconductor MA31750 is a single-chip microprocessor that implements the full MIL-STD-1750A instruction set architecture, or Option 2 of Draft MIL-STD1750B. The processor executes all mandatory instructions and

Contextual Info: PjjpH GEC P L E S S E Y PRELIMINARY INFORMATION DS3748-4.2 MA31750 HIGH PERFORMANCE MIL-STD-1750 MICROPROCESSOR The GEC Plessey MA31750 is a single-chip microprocessor that implements the full MIL-STD-1750A instruction set architecture, or Option 2 of Draft MIL-STD1750B. The processor executes all mandatory instructions and

MA31750 processor architecture

Abstract: D100D MA31750 D200D 1750A processor architecture MA31750 architecture mil-std-1750 nte 4006 MAS281 MIL-STD-1750* BX
Contextual Info: MA31750 MA31750 High Performance MIL-STD-1750 Microprocessor Replaces July 2002 version, DS3748-8.1 DS3748-8.2 Feb 2006 LN24435 The Dynex Semiconductor MA31750 is a single-chip microprocessor that implements the full MIL-STD-1750A instruction set architecture, or Option 2 of Draft MIL-STD1750B. The processor executes all mandatory instructions and

MA31750 processor architecture

Abstract: MA31750 a006 MA31751 MAS281 N4211 1750A processor architecture
Contextual Info: MA31750 MA31750 High Performance MIL-STD-1750 Microprocessor Replaces January 2000 version, DS3748-8.0 DS3748-8.1 July 2002 The Dynex Semiconductor MA31750 is a single-chip microprocessor that implements the full MIL-STD-1750A instruction set architecture, or Option 2 of Draft MIL-STD1750B. The processor executes all mandatory instructions and

Contextual Info: P B t i GEC plessey PRELIMINARY INFORMATION DS3748-2.2 June 1993 JMA31750 HIGH PERFORMANCE MIL-STD-1750 MICROPROCESSOR The G EC P le s s e y M A 31 750 is a s in g le -c h ip microprocessor that implements the full MIL-STD-1750A instruction set architecture, or Option 2 of Draft MIL-STD1750B. The processor executes all mandatory instructions and