15NST Search Results

Contextual Info: COM’L: -15/20 a MACH230-15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 128 Macrocells ■ 128 Flip-flops; 4 clock choices ■ 15nstPD ■ 8 “PAL26V16” blocks with burled macrocells

Contextual Info: FINAL COM’L: -15/20, Q-25 a MACH435-15/20, Q-25 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins in PLCC ■ Up to 20 product terms per function, with XOR ■ 128 Macrocells ■ Flexible clocking ■ 15nstpo

PAL26V16

Abstract: teradyne lasar
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 Z I Advanced Micro Devices M A C H 1 3 0 - 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 64 Macrocells ■ 64 Flip-flops; 4 clock choices ■ 15 ns tpD Commercial

Contextual Info: P R E L IM IN A R Y COM’L: -15/20 M A C H 4 6 5 -1 5 /2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 208 pins In PQFP ■ Up to 20 product terms per function, with XOR ■ JTAG, 5-V, In-circult programmable

Contextual Info: COM’L: H-15 ZI Advanced Micro Devices PALCE20RA1 OH-15 24-pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • ■ Programmable replacement for high-speed CMOS orTTL logic TTL-level register preload for testability Easy design with PALASM software

2SK582

Abstract: 2SK600 2SK581 2SK609 2SK610 2SK606 2SK603 2sk611 2SK590 2SK604
Contextual Info: 56 - f m & ffl tt £ & m ft K 2SK578 £ X V* it ? Jk V fë [* * £* (V) H E Pp/PcH (A) * (max) (A) (W) & <Ta=25eO) ¥f m I g ss Vg s (V) (min) (max) Vds (A) (A) (V) (min) (max) Vds (V) (V) (V) (min) (S) Id (A) •—Vt - Id (A) HS PSW MOS N E 150 DSS

Contextual Info: COM’L: -15/20 il Advanced Micro Devices M A C H L V 2 1 0 - 1 5 /2 0 High Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • ■ 50 MHz max external Low-voltage operation, 3.3-V JEDEC compatible ■ 38 Inputs with advanced pull-up/pull-down

Contextual Info: INTEGRATED CIRCUITS m m s ^ e eI It Xiiinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family, For more technical or sales information, please see: www.xilinx.com XCR5128 128 macrocell CPLD Product specification Supersedes data of 1997 Aug 12

Contextual Info: INTEGRATED CIRCUITS im m l y i E I TI Xilinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family, For more technical or sales information, please see: www, xilin i* com XCR3128 128 macrocell CPLD Product specification Supersedes data of 1997 Aug 12

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

Contextual Info: Product specification Philips Semiconductors 128 macrocell CPLD with enhanced clocking PZ5128C/PZ5128N FEATURES DESCRIPTION • Industry’s first TotalCMOS PLD - both CMOS design and process technologies The PZ5128C/PZ5128N CPLD Complex Programmable Logic

Contextual Info: FINAL COM’L: -15/20 IND:-18/24 S M A C H 1 2 0 - 1 5 / 2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 68 Pins ■ 56 Inputs ■ 48 Macrocells ■ 48 Outputs ■ 15 ns tpoCommercial 18 ns tpo Industrial

Contextual Info: COM’L MIL a PAL16R8 Family Advanced Micro Devices 20-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 7.5 ns maximum propagation delay ■ Easy design with PALASM software ■ Popular 20-pln architectures: 16L8,16R8, 16R6,16R4

PAL22V10

Abstract: PD3024 DAL22V10 AMPAL22V10/A february 1996
Contextual Info: COM’L: -7/10/15 PAL22V10 Family, AmPAL22V10/A 24-Pin TTL Versatile PAL Device Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • As fast as 7.5-ns propagation delay and 91 MHz fMAX external ■ 10 Macrocells programmable as registered or combinatorial, and active high or active low to

mach355-20yc

Abstract: mach 3 family amd mach355
Contextual Info: FINAL COM’L: -15/20 a Advanced Micro Devices MACH355-15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 144 Pins in PQFP ■ Up to 20 product terms per function, with XOR ■ JTAG, 5-V, in-circuit programmable ■ Flexible clocking

pal 007a

Abstract: MACH21D PAL 006A PAL 002a pal 005a MACH110 MACH210 MACH215 PAL22V10 PAL22V16
Contextual Info: FINAL COM’L: -7/10/12/15/20, Q-12/15/20 IND: -12/14/18/24 M ACH21OA-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20 a Advanced Micro Devices High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • Peripheral Component Interconnect PCI compliant

JEDEC B12-43

Abstract: pal 002 PZ3128 PZ5128 PZ5128IS15A84 PZ5128-S10A84 PZ5128-S10BB1 PZ5128-S12A84 PZ5128-S12BB1 PZ5128-S7A84
Contextual Info: Philips Sem iconductors Product specification 128 macrocell CPLD PZ5128 Table 1. PZ5128 Features FEATURES • Industry’s first TotalCMOS PLD - both CMOS design and process technologies PZ5128 Usable gates • Fast Zero Power FZP™ design technique provides ultra-low

Power and Industrial Semiconductors

Contextual Info: Philips Semiconductors Product specification 64 macrocell CPLD PZ3064 FEATURES DESCRIPTION • Industry’s first TotalCMOS PLD - both CMOS design and process technologies The PZ3064 CPLD Complex Programmable Logic Device is the second in a family of Fast Zero Power (FZP™) CPLDs from Philips

Contextual Info: MACH120-15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 68 Pins 56 Inputs ■ 48 Macrocells 48 Outputs ■ 15 ns tpD Commercial 20 ns tpo Military 48 Flip-flops; 4 clock choices ■ 50 MHz fMAx Commercial

Contextual Info: A D V A N C E IN F O R M A T IO N C O M ’L: -15/20 MACH465-15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 196 pins in PQFP ■ Up to 20 product term s per function, w ith XOR ■ 256 m acrocells ■ Flexible clocking

RAL22V10

Abstract: PALCE22V100-25 pal22v10
Contextual Info: COM’L MIL Cl PAL22V10-10/15 AmPAL22Vl 0/A PALCE22V10H-15/25/Q-25 Advanced Micro Devices 24-pln TTUCMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS • As fast as 10 ns propagation delay and 71 MHz fM AX ■ Low-power EE CMOS versions ■ 10 m acrocells program m able as registered o r

mach 1 family amd

Abstract: MACH110
Contextual Info: Advanced Micro Devices MACH 1 and 2 Device Families High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • High-performance, high-density, electrically-erasable CMOS PLD families ■ ■ 900 to 3600 PLD gates ■ 44 to 84 pins in cost-effective PLCC and CQFP

Contextual Info: COM’L AmPAL18P8B/AL/A/L Advanced Micro Devices 20-Pin Combinatorial TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 15 ns maximum propagation delay ■ Universal combinatorial architecture ■ Programmable output polarity ■ Programmable replacement for high-speed

Contextual Info: ADVANCE INFORMATION COM’L: -15/20 Advanced Micro Devices MACH355-15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 132 Pins In PQFP ■ Flexible clocking ■ 96 Macrocells — Four global clock pins with selectable edges — Asynchronous mode available for each