02S7S2L Search Results

htw 323

Abstract: plji palce programming algorithm
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25. Q-20/25 MIL: H-15/20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all GAL 20V8/AS ■ Electrically erasable CMOS technology pro­

Contextual Info: COM’L: H-25 H Advanced Micro Devices PALCE29M16H-25 24-Pin EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • High-performance semicustom logic replacement; Electrically Erasable EE technology allows reprogrammability Register/Latch Preload permits full logic

Contextual Info: FINAL COM’L: -12/15/20 IND: 14/18/24 a MACH110-12/15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 38 Inputs ■ 32 Macrocells ■ 32 Outputs ■ 12 n s t P D Commercial 14 nstpD Industrial

Contextual Info: FINAL COM’L: -12/15/20 ZI M A C H 4 4 5 - 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 100-pin version of the MACH435 in PQFP Up to 20 product terms per function, with XOR ■ 5 V, in-circuit programmable

Contextual Info: FINAL COM’L: -15/20 IND:-18/24 S M A C H 1 2 0 - 1 5 / 2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 68 Pins ■ 56 Inputs ■ 48 Macrocells ■ 48 Outputs ■ 15 ns tpoCommercial 18 ns tpo Industrial

Contextual Info: F IN A L COM’L: -12/15/20 IND: -14/18/24 MACH215-12/15/20 High-Density EE CMOS Programmable Logic a Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ 32 Output Macrocells ■ ■ ■ ■ 67 MHz fMAx external Commercial 42 MHz fMAx external Industrial

Contextual Info: COM’L: -10 & Advanced Micro Devices P A L L V 1 6 V 8 - 1 0 Low-Voltage 20-Pin EE CMOS Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS Low-voltage operation, 3.3 V JEOEC compatible • Programmable output polarity — Vcc = +3.0 V to +3.6 V

Contextual Info: COM’L: H-25 Advanced Micro Devices PALCE29M A16H-25 24-Pin EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS • High-performance semicustom logic replacement; Electrically Erasable EE technology allows reprogrammability ■ 16 bidirectional user-programmable I/O logic

pal22v10

Abstract: AMPAL22V10APC
Contextual Info: COM’L :-7/10/15 MIL: -12/20 a Advanced Micro Devices PAL22V10 Family, AmPAL22V10/A 24-Pin TTL Versatile PAL Device DISTINCTIVE CHARACTERISTICS • As fast as 7.5 ns propagation delay and 91 MHz fMAx external ■ 10 Macrocells programmable as registered or

pal 007a

Abstract: MACH21D PAL 006A PAL 002a pal 005a MACH110 MACH210 MACH215 PAL22V10 PAL22V16
Contextual Info: FINAL COM’L: -7/10/12/15/20, Q-12/15/20 IND: -12/14/18/24 M ACH21OA-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20 a Advanced Micro Devices High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • Peripheral Component Interconnect PCI compliant

xc2064 pcb

Abstract: Y148 K6A60 XC-2064-50 XC2018-50
Contextual Info: ADV M C R O PLA/PLE/ARRAYS „ E „ | H n 5 a g | Logic Cell Array M 2 0 6 4 /M 2 0 1 8 Features/Benefits USER l/Os CONFIG­ URATION PROGRAM BITS • Completely reconflgurable by the user In the final system LOGIC CONFIG­ CAPACITY URABLE PART NUMBER (USABLE

AMD K6

Contextual Info: ADV MI C R O PLA/PLE/ARRAYS 13E' D | 0 2 5 7 5 2 b 0 0 2 3 7 7 3 ñ 3000 SERIES FAMILY OF PROGRAMMABLE GATE ARRAYS PRELIM INARY D ISTIN C TIVE * • ♦ • C H A R AC TERISTIC S Second generation user-programmable gate • array • Flexible array architecture

MACH210

Contextual Info: FINAL COM’L: -7/10/12/15/20, Q-12/15/20 a IND: -12/14/18/24 MACH21OA-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20 Advanced Micro Devices High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Peripheral Component Interconnect PCI

Contextual Info: COM’L: -12 a Advanced Micro Devices M A C H 1 2 0 -1 2 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 68 Pins ■ 48 Outputs ■ 48 Macrocells ■ 48 Flip-flops; 4 clock choices ■ 12nstro ■ 4 PAL blocks ■ 66.7 MHz max external

Contextual Info: a Advanced Micro Devices MACH230-10 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 128 Macrocells ■ ■ 10nstPD ■ 8 “PAL26V16” blocks with buried macrocells ■ 77 MHz Imax ■ external 128 Flip-flops; 4 clock choices

palce16v8h-15

Abstract: palce16v8 programming algorithm
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25,0-20/25 PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all 20-pin GAL devices ■ Programmable output polarity

PAL16l8 MMI

Abstract: pal16r8b PAL16R8 MMI AMD 16L8 PAL16R4
Contextual Info: COM’L: -4/5/7/B/B-2/A, D/2 MIL: -10/12/B/B-2/A/B-4 Advanced Micro Devices PAL16R8 Family 20-Pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • As fast as 4.5 ns maximum propagation delay ■ Power-up reset for initialization ■ Popular 20-pin architectures: 16L8,16R8,16R6,

Contextual Info: IND: -20 Advanced Micro Devices PALLV16V8Z-20 Low-Voltage, Zero-Power, 20-Pin EE CMOS Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Low-voltage operation, 3.3 V JEDEC compatible ■ Direct plug-in replacement for the PAL16R8 series and most of the PAL10H8 series

Contextual Info: COM’L: -7/10/15 PALLV22V10 Family Low-Voltage 24-Pin EE CMOS Versatile PAL Device & Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Low-voltage operation, 3.3 V JEDEC compatible — Vcc = + 3.0 V to 3.6 V ■ Commercial operating temperature range

PAL24V10

Contextual Info: COM’L: H-15/25 ry Advanced Micro Devices PALCE24V1 OH-15/25 EE CMOS 28-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Electrically erasable CMOS technology provides reconfigurable logic and full testability ■ High speed CMOS technology

MACH465

Abstract: MACH465-12 MACH465-15 ge-57
Contextual Info: FINAL M A C H 4 6 COM’L: -12/15/20 5 - 1 2 / 1 5 / 2 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 208 pins in PQFP ■ Up to 20 product terms per function, with XOR ■ JTAG, 5-V, in-circuit programmable

ce20V8

Abstract: PALCE20V8H5JC5 GAL20V8 PAL20R8 PALCE20V8 AMD TOP-SIDE MARKING
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic z\ Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all GAL 20V8/As ■ Electrically erasable CMOS technology pro­