XILINX LOGICORE CORE DDS Search Results

XILINX LOGICORE CORE DDS Result Highlights (5)

Part	ECAD Model	Manufacturer	Description	Download	Buy
TMPM330FWFG		Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/LQFP100-P-1414-0.50H	Datasheet
TMPM367FDXBG		Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/TFBGA109-P-0909-0.65	Datasheet
TMPM373FWDUG		Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/LQFP48-P-0707-0.50C	Datasheet
TMPM068FWXBG		Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M0 Core Based Microcontrollers/32bit/P-VFBGA57-0505-0.50-001	Datasheet
TMPM3HLFDAUG		Toshiba Electronic Devices & Storage Corporation	Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP64-1010-0.50-003	Datasheet

XILINX LOGICORE CORE DDS Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
fir compiler v5 Abstract: fir compiler xilinx XC6SLX150-2FGG484 Polyphase Filter Banks 90CLK fir compiler v4 digital FIR Filter VHDL code polyphase FIR filter interpolation matlaB simulink design FDATOOL verilog code for interpolation filter Contextual Info: FIR Compiler v5.0 DS534 June 24, 2009 Product Specification Introduction Overview The Xilinx LogiCORE IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters utilizing either Multiply-Accumulate MAC or	Original	ds534 fir compiler v5 fir compiler xilinx xc6slx150-2fgg484 +7polyphase filter banks 90clk fir compiler v4 digital fir filter vhdl code polyphase fir filter interpolation matlab simulink design fdatool verilog code for interpolation filter	PDF
fir compiler v5 Abstract: ds534 DSP48 SRL16 XIP162 matched filter matlab codes fir compiler xilinx digital FIR Filter using distributed arithmetic MATLAB code for halfband filter fir compiler v4 Contextual Info: FIR Compiler v3.2 DS534 October 10, 2007 Product Specification Features General Description • Highly parameterizable drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, The Xilinx LogiCORE™ IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters	Original	ds534 fir compiler v5 dsp48 srl16 +6xip162 matched filter matlab codes fir compiler xilinx digital fir filter using distributed arithmetic matlab code for halfband filter fir compiler v4	PDF
XC7VH580T-HCG1155-2 Contextual Info: v LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers v2.0 DS878 December 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The customizable LogiCORE IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series	Original	ds878 xc7vh580t-hcg1155-2	PDF
MZ80 sensor Abstract: crt monitor circuit diagram intex 171 8086 microprocessor based project on weight AT89C51 opcode SL100 pin configuration interfacing Atmel 89C51 with ir sensors Block Diagram of 8279 micro processor generation of control signals in 89c51 micro keypad 4x6 matrix led interfacing with 89C51 Contextual Info: R 1. Introduction 2. LogiCORE Products 3. AllianceCORE Products 4. LogiBLOX 5. Reference Designs Section Titles R Table of Contents Introduction Introduction Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2	Original	xc4000-series xc3000 xc4000 xc5000 +13xapp028 xapp028v xapp028o mz80 sensor crt monitor circuit diagram intex 171 8086 microprocessor based project on weight at89c51 opcode sl100 pin configuration interfacing atmel 89c51 with ir sensors block diagram of 8279 micro processor generation of control signals in 89c51 micro keypad 4x6 matrix led interfacing with 89c51	PDF
Contextual Info: LogiCORE IP ChipScope Pro IBERT for 7 Series GTH Transceivers v2.01a DS873 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The customizable LogiCORE IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series	Original	ds873	PDF
UG331 Abstract: CWda04 XAPP256 manual SPARTAN-3 XC3S400 evaluation kit vhdl code for rs232 receiver hcl l21 usb power supply circuit diagram hcl p38 CIRCUIT diagram R80515 XC3SD1800A-FG676 vhdl ethernet spartan 3a Contextual Info: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.6 December 3, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development	Original	ug331 guides/ug332 cwda04 xapp256 +7manual spartan-3 xc3s400 evaluation kit vhdl code for rs232 receiver hcl l21 usb power supply circuit diagram hcl p38 circuit diagram r80515 xc3sd1800a-fg676 vhdl ethernet spartan 3a	PDF
uart 16550 Abstract: XC6SLX16CSG324 AMBA AXI4 XC6SLX16-CSG324 XC6VLX75T-FF784 uart vhdl fpga UART16550 V6 6D XC7V855T National Semiconductor PC16550D UART Contextual Info: LogiCORE IP AXI UART 16550 v1.01a DS748 June 22, 2011 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA (Advance Microcontroller Bus Architecture) AXI (Advanced	Original	ds748 pc16550d uart 16550 xc6slx16csg324 +8amba axi4 xc6slx16-csg324 xc6vlx75t-ff784 uart vhdl fpga uart16550 v6 6d xc7v855t national semiconductor pc16550d uart	PDF
Contextual Info: LogiCORE IP Multi-Port Memory Controller v6.06.a DS643 February 22, 2013 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Multi-Port Memory Controller (MPMC) is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR	Original	ds643 ppc440mc	PDF
xilinx logicore core dds Abstract: vhdl code dds vhdl code for msk modulation spartan 3a EP-2000 018HZ phase shift keying vhdl code for accumulator DS558 DSP48 Contextual Info: DDS Compiler v2.0 DS558 May 17, 2007 Product Specification Features Applications • Drop-in module for Virtex -II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-3, Spartan-3A, Spartan-3A DSP, and Spartan-3E FPGAs • Digital radios and modems • Software-defined radios SDR	Original	ds558 dsp48 xilinx logicore core dds vhdl code dds +6vhdl code for msk modulation spartan 3a ep-2000 018hz phase shift keying vhdl code for accumulator	PDF
sine cosine phase quadrant look-up address Abstract: PHASE SHIFT KEYING PSK precision Sine Wave Generator xilinx logicore core dds is706 quadrature phase sine wave generator 2061d DAC 5754 FPGA FAMILY direct digital synthesizer precision waveform generator Contextual Info: Direct Digital Synthesizer DDS V4.0 October 4, 2001 Product Specification • • Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com • • Applications	Original	1614db pr-2001 sine cosine phase quadrant look-up address phase shift keying psk +8precision sine wave generator xilinx logicore core dds is706 quadrature phase sine wave generator 2061d dac 5754 fpga family direct digital synthesizer precision waveform generator	PDF
verilog code for fir filter using DA Abstract: 4 tap fir filter based on mac vhdl code polyphase interpolator design in verilog verilog code for interpolation filter verilog code for decimation filter image video procesing code VHDL code for polyphase decimation filter VHDL code for polyphase decimation filter using D verilog code for decimator fir compiler xilinx Contextual Info: Distributed Arithmetic FIR Filter v8.0 DS240 v1.0 March 28, 2003 Features General Description • Drop-in module for Virtex , Virtex-E, Virtex-II, Virtex-II Pro™, Spartan™-II, Spartan-IIE, and Spartan-3 FPGAs • High-performance finite impulse response (FIR),	Original	ds240 32-bit verilog code for fir filter using da 4 tap fir filter based on mac vhdl code +8polyphase interpolator design in verilog verilog code for interpolation filter verilog code for decimation filter image video procesing code vhdl code for polyphase decimation filter vhdl code for polyphase decimation filter using d verilog code for decimator fir compiler xilinx	PDF
xilinx logicore core dds Abstract: polyphase interpolator design in verilog matched filter in vhdl 8 tap fir filter vhdl OPTIMIZED FPGA IMPLEMENTATION OF MULTI-RATE FIR F FIR FILTER implementation xilinx hilbert FIR FILTER implementation on fpga 11-TAP fir compiler Contextual Info: Distributed Arithmetic FIR Filter V4.0.0 November 3 2000 Product Specification Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 FAX: +1 408-559-7114 URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com 1 Features • • •	Original	2-to-1024 1-to-32 xilinx logicore core dds polyphase interpolator design in verilog +8matched filter in vhdl 8 tap fir filter vhdl optimized fpga implementation of multi-rate fir f fir filter implementation xilinx hilbert fir filter implementation on fpga 11-tap fir compiler	PDF
four way traffic light controller vhdl coding Abstract: PEB20324 Microtec Research mcc960 vhdl code for traffic light control X4013 vhdl code for rs232 receiver vhdl code for TRAFFIC LIGHT CONTROLLER SINGLE WAY vhdl code rs232 v.110 QuadFALC EASY324 Contextual Info: T o o l D e s c ri p t i o n , D S 1 , O c t o b e r 2 0 0 0 EA S Y 3 2 4 - R 2 Reference Design for MUNICH128x and QuadFALC Datacom N e v e r s t o p t h i n k i n g . Edition 10.00 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany	Original	munich128x d-81541 four way traffic light controller vhdl coding peb20324 +8microtec research mcc960 vhdl code for traffic light control x4013 vhdl code for rs232 receiver vhdl code for traffic light controller single way vhdl code rs232 v.110 quadfalc easy324	PDF