WP1A Search Results

AxC11

Contextual Info: N EC ELECTRONICS INC dEEC ^ t 7 E 1 • tMS7S2S DG3R58b MM3 H N E C E _ 16Mbit Synchronous DRAM_ CONTENTS Programable 3 - stage pipeline. Features.

A8RN

Abstract: uPD4502161 D4502161
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT ju P D 4 5 0 2 1 6 1 2M-bit Synchronous DRAM Description The /¿PD4502161 is a high-speed 2,097,152-bit synchronous dynamic random-access memory, organized as 65,536 x 16 x 2 word x bit x bank , respectively. The synchronous DRAM achieves high-speed data transfer using the pipeline architecture.

Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT M PD4516421,4516821,4516161 16M bit Synchronous DRAM Description The UPD4516421, UPD4516821, uPD 4516161 are high-speed 16 777 2 1 6-bit synchronous dynamic random-access memories, each organized as 2 097 152-word x

transistor yk

Abstract: FZ1800R12HP4_B9 2sd88
Contextual Info: Technische Information / technical information FZ1800R12HP4_B9 IGBT-Module IGBT-modules IHM-B Modul mit soft schaltendem Trench-IGBT4 IHM-B module with soft-switching Trench-IGBT4 Vorläufige Daten / preliminary data +,-. / ! + , 012 / ! 3 4 ,56 / $ Typische Anwendungen

PD48

Abstract: uPD481850GF-A12-JBT
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD481850 8M-bit Synchronous GRAM Description The µPD481850 is a synchronous graphics memory SGRAM organized as 128 K words x 32 bits × 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write

uPD481850

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD481850 8 M-bit Synchronous GRAM for Rev.L Description The µPD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits × 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD4516421-PC, 4516821-PC, 4516161-PC 16M-bit Synchronous DRAM for PC SDRAM Lite Description The µPD4516421-PC, 4516821-PC, 4516161-PC are high-speed 16,777,216-bit synchronous dynamic randomaccess memories, organized as 2,097,152 x 4 × 2, 1,048,576 × 8 × 2 and 524,288 × 16 × 2 word × bit × bank ,

UPD4502161

Abstract: upd4502161g5a12 UPD4502161G5A12-7JF PD4502161 BD3/1/TX13/7.9/PP10/UPD4516421G5-A12-7JF
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD4502161 2M-bit Synchronous DRAM Description The µPD4502161 is a high-speed 2,097,152-bit synchronous dynamic random-access memory, organized as 65,536 x 16 × 2 word × bit × bank , respectively. The synchronous DRAM achieves high-speed data transfer using the pipeline architecture.

NEC uPD 688

Abstract: CQ-111
Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT /i PD4516421,4516821,4516161 16M bit Synchronous DRAM Description The UPD4516421, UPD4516821, uPD 4516161 are high-speed 16 777 216-bit synchronous dynamic random-access memories, each organized as 2 097 152-word x

WP1F

Abstract: CMOS blemish specification QCIF LR38630 LZ34C10
Contextual Info: LR38630 Digital Signal Processor for CIF CMOS Image Cameras LR38630 DESCRIPTION The LR38630 is a CMOS digital signal processor for color camera systems of 110 k-pixel CMOS image sensor with primary color mosaic filters. The camera system consists of CIF CMOS image

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT JuPD4502161 2M-bit Synchronous DRAM Description The ¿¡PD4502161 is a high-speed 2,097,152-bit synchronous dynam ic random -access memory, organized as 65,536 x 16 x 2 word x bit x bank , respectively. The synchronous DRAM achieves high-speed data transfer using the pipeline architecture.

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD4516421, 4516821, 4516161 16M-bit Synchronous DRAM D escrip tio n The /iPD4516421, 4516821, 4516161 are high-speed 16,777,216-bit synchronous dynam ic random-access m em ories, organized as 2,097,152x4x2, 1,048,576x8x2 and 524,288x16x2 w ordxbitxbank , respectively.

a2-xqa

Abstract: IC-3394
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT juPD 4516421 , 4516821 , 4516161 16M-bit Synchronous DRAM Description The ¿iPD4516421, 4516821, 4516161 are high-speed 16,777,216-bit synchronous dynamic random-access memories, organized as 2,097,152 x 4 x 2,1,048,576 x 8 x 2 and 524,288 x 16 x 2 word x bit x bank , respectively.

FZ1200R12HP4

Contextual Info: Technische Information / technical information FZ1200R12HP4 IGBT-Module IGBT-modules IHM-B Modul mit soft schaltendem Trench-IGBT4 IHM-B module with soft-switching Trench-IGBT4 Vorläufige Daten / preliminary data +,-. / ! , 012 / ! Typische Anwendungen •8

Contextual Info: PRELIMINARY DATA SHEET_ MOS INTEGRATED CIRCUIT jUPD4811650 for Rev.E 16 M-BIT SYNCHRONOUS GRAM 256K-WORD BY 32-BIT BY 2-BANK Description The ,uPD4811650 is a synchronous graphics memory SGRAM organized as 262,144 words x 32 bits x 2 banks

M12939EJ3V0DS00

Abstract: uPD4516421AG5-A10B-9NF uPD4516821AG5-A10-9NF uPD4516161AG5-A10B-9NF 4516161a PD4516821
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD4516421A, 4516821A, 4516161A for Rev.P 16M-bit Synchronous DRAM 2-banks, LVTTL 2 Description The µPD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access memories, organized as 2,097,152 x 4 × 2, 1,048,576 × 8 × 2, 524,288 × 16 × 2 (word × bit × bank , respectively.

uPD4504161

Abstract: upd4504161g5
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4504161 4M-bit Synchronous DRAM Description The µPD4504161 is a high-speed 4,194,304-bit synchronous dynamic random-access memory, organized as 131,072 x 16 × 2 word × bit × bank , respectively. The synchronous DRAM achieves high-speed data transfer using the pipeline architecture.

UPD4504161

Abstract: PD4504161 upd4504161g5
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4504161 4M-bit Synchronous DRAM Description The µPD4504161 is a high-speed 4,194,304-bit synchronous dynamic random-access memory, organized as 131,072 x 16 × 2 word × bit × bank , respectively. The synchronous DRAM achieves high-speed data transfer using the pipeline architecture.

nec eric-2

Abstract: UPD481
Contextual Info: PRELIMINARY DATA SHEET NEC / MOS INTEGRATED CIRCUIT ¿¿PD4 8 1 8 5 0 8 M-bit Synchronous GRAM for Rev.L Description The /jPD 481 850 is a synchrono us graphics m em o ry SG R AM organized as 131,072 w ords x 32 b its x 2 banks random access port. T his device can ope rate up to 100 M Hz b y using synchronous interface.

PD481850GF

Abstract: D481850
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD 481850 8M-bit Synchronous GRAM Description The iiPD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits x 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write function

NEC uPD

Abstract: NEC AND 1994 AND sdram
Contextual Info: • b4B ?S 5S 0041123 S 34 ■ PRELIMINARY DATA SHEET_ M O S IN T E G R A T E D C IR C U IT M PD4516421,4516821,4516161 16M bit Synchronous DRAM Description The uPD4516421, uPD4516821, uPD 4516161 are high-speed 16 777 216-bit synchronous dynamic random-access memories, each organized as 2 097 152-word x

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT ^ 0 4 8 1 8 5 0 for Rev.L 8 M-BIT SYNCHRONOUS GRAM 128K-WORD BY 32-BIT BY 2-BANK Description The ,uPD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits x 2 banks random access port.

A91A

Abstract: uPD4516161AG5-A10-9NF nec 44pin NEC 4516821 TNC 24 mk 2 uPD4516161AG5-A80-9NF uPD4516161AG5-A10 NEC MEMORY
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD4516421A, 4516821 A, 4516161A 16M-bit Synchronous DRAM Description The ¿¡PD4516421 A, 4516821 A, 4516161A are high-speed 16,777,216-bit synchronous dynam ic random -access mem ories, organized as 2,097,152 x 4 x 2, 1,048,576 x 8 x 2 and 524,288 x 16 x 2 word x bit x bank , respectively.

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4811650 for Rev.E 16 M-BIT SYNCHRONOUS GRAM 256K-WORD BY 32-BIT BY 2-BANK Description The µPD4811650 is a synchronous graphics memory SGRAM organized as 262,144 words x 32 bits × 2 banks random access port.