NEC marking code A4X
Abstract: 2XD marking
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT 8M-bit Synchronous GRAM Description The //PD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits x 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write function
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upd481850100-pins100gf-65-jbtpd481850+4/xpd481850pd481850gf-jbtnec marking code a4x2xd marking
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Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ¿¿PD4 8 1 8 5 0 8M-bit Synchronous GRAM Description The ^PD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits x 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write function
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pd481850100-pinf-65-jbupd481850+1pd481850gf-jbt
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PD48
Abstract: uPD481850GF-A12-JBT
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD481850 8M-bit Synchronous GRAM Description The µPD481850 is a synchronous graphics memory SGRAM organized as 128 K words x 32 bits × 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write
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pd481850100-pinpd48upd481850gf-a12-jbt |
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D481850
Abstract: NEC D481850 D481
Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT 481850 ¿ ÎP D 8M-bit Synchronous GRAM Description The ¿¿PD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits x 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write function
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upd481850100-pins100gf-65-jbtjupd481850+4mpd481850gf-jbtd481850nec d481850d481
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PD48
Abstract: PD481850 lm 512
Contextual Info: DATA SHEET DATA SHEET MOS INTEGRATED CIRCUIT µPD481850 8M-bit Synchronous GRAM Description The µPD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits × 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write function
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pd481850100-pins100gf-65-jbtpd481850gf-jbt+2pd48lm 512
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nec eric-2
Abstract: UPD481
Contextual Info: PRELIMINARY DATA SHEET NEC / MOS INTEGRATED CIRCUIT ¿¿PD4 8 1 8 5 0 8 M-bit Synchronous GRAM for Rev.L Description The /jPD 481 850 is a synchrono us graphics m em o ry SG R AM organized as 131,072 w ords x 32 b its x 2 banks random access port. T his device can ope rate up to 100 M Hz b y using synchronous interface.
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s100gf-65-jbtupd481850pd481850/jpd481650gf-jbt+3100-pinnec eric-2upd481
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uPC2581
Abstract: uPC2002 2sd1557 uPA67C uPB582 upc1237 uPC317 2P4M PIN DIAGRAM 2SC4328 uPC157
Contextual Info: C&C for Human Potential Microcomputer 1 SEMICONDUCTOR SELECTION GUIDE GUIDE BOOK IC Memory 2 Semi-Custom IC 3 Particular Purpose IC 4 General Purpose Linear IC 5 Transistor / Diode / Thyristor 6 Microwave Device / Consumer Use High Frequency Device 7 Optical Device 8
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pd7500x10679ejav0sg00mf-11341995p+10upc2581upc20022sd1557upa67cupb582upc1237upc3172p4m pin diagram2sc4328upc157
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PD481850GF
Abstract: D481850
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD 481850 8M-bit Synchronous GRAM Description The PD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits x 2 banks random access port. This device can operate up to 100 MHz by using synchronous interface. Also, it has 8-column Block Write function
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upd481850100-pin-613i8-787io+7s1000f-w-jbtb4e7525ddb3t73ppd481850/1pd481850gf-jbtpd481850gfd481850
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Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT ^ 0 4 8 1 8 5 0 for Rev.L 8 M-BIT SYNCHRONOUS GRAM 128K-WORD BY 32-BIT BY 2-BANK Description The ,PD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits x 2 banks random access port.
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128k-word32-bitupd481850100-pin+4s100gf-65-jbtjupd481850pd481850pd481850gf-jbt
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D481850G
Abstract: t838 D481850
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT ¿ P D 481850 f o r R e v . L 8 M-BIT SYNCHRONOUS GRAM 128K-WORD BY 32-BIT BY 2-BANK Description The /¿PD481850 is a synchronous graphics memory (SGRAM organized as 131,072 words x 32 bits x 2 banks random access port.
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128k-word32-bitupd481850100-pin+3d481850gt838d481850
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