TXC 6M Search Results

cbda c28

Contextual Info: ASPEN Device CellBus Access Processor TXC-05810 DATA SHEET DESCRIPTION FEATURES • TranSwitch CellBus switch fabric compliant, interoperable with CUBIT-Pro TXC-05802 and TXC-05802B and CUBIT-3 (TXC-05804) • RISC-based hardware architecture

IT16B

Abstract: TXC-05810AIEB lscan1
Contextual Info: CellBus ASPEN Device Access Processor TXC-05810 DATA SHEET DESCRIPTION  • TranSwitch CellBus switch fabric compliant, interoperable with CUBIT-Pro TXC-05802 and TXC-05802B and CUBIT-3 (TXC-05804) • RISC-based hardware architecture •

SARA-S

Abstract: vlsi TXC-05501 SYN155C TXC-02050 TXC-05601 sara-r TXC-99002-MC
Contextual Info: SARA-S and SARA-R Devices ATM/SMDS Segmentation Controller, TXC-05501 ATM/SMDS Reassembly Controller, TXC-05601 m/ibOu PRODUCT INFORMATION FEATURES DESCRIPTION • SARA-S Segmentation Controller TXC-05501 segments packets into ATM/SMDS cells, up to 8000

Contextual Info: SARA-S and SARA-R Devices ATM/SMDS Segmentation Controller, TXC-05501 ATM/SMDS Reassembly Controller, TXC-05601 VW PRODUCT INFORMATION FEATURES DESCRIPTION • SARA-S Segmentation Controller TXC-05501 segments packets into ATM/SMDS cells, up to 8000 simultaneously

TXC-02050

Abstract: 21047 circuit diagram for computer
Contextual Info: JT2F-MRT Evaluation Board JT2 Framer and Line Interface TXC-21047 PRODUCT INFORMATION FEATURES DESCRIPTION • Complete single-board test system for evaluating TranSwitch JT2F and MRT VLSI devices operating at 6 Mbit/s: - JT2F: 6 Mbit/s Framer Device TXC-03702

2RD6

Abstract: RB35 TDNB0
Contextual Info: BACK HDLC Device HDLC Controller TXC-05101C DATA SHEET Preliminary FEATURES DESCRIPTION • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send

RB35

Abstract: TB28 hdlc CRC16 CRC-16 CRC-32 TB31 TB32 RXB 17-18
Contextual Info: HDLC Device HDLC Controller TXC-05101C DATA SHEET Preliminary FEATURES DESCRIPTION • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send

Contextual Info: HDLC Device HDLC Controller TXC-05101C DATA SHEET Preliminary = DESCRIPTION — The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send and receive packets at line rates up to 51.84 Mbit/s using either a nibble, byte-parallel, or serial interface.

TXC-06010-MB

Abstract: TXC-06010 samsung Capacitance lables transwitch packettrunk fifo synchronus asynchronus PacketTrunk
Contextual Info:  PacketTrunk-4 Plus Device TDMoIP/MPLS Gateway Device TXC-06010 DATA SHEET PRODUCT PREVIEW TXC-06010-MB, Ed. 2 June 2006 FEATURES APPLICATIONS • Four T1/E1/Serial or one T3/E3 TDM interfaces • One 10/100 Ethernet IEEE 802.3 MAC interface via MII/RMII/SMII/SSMII; HDX or

Contextual Info: t h a n S w it c h , E 1 M x 1 6 D e v ic e E1 Mapper 16-Channel TXC-04216 X- TECHNICAL OVERVIEW PRODUCT PREVIEW DESCRIPTION The E1Mx16 bus interface is used to connect to other TranSwitch devices such as the STM-1/STS-3/STS-3C Overhead Terminator PHAST-3N , TXC-06103, to form

STM CL-80

Abstract: acp ca14 AD10 AD14 TXC-05551
Contextual Info: SARA-2 ATM Cell Processing 1C Device TXC-05551 DATA SHEET PRODUCT PREVIEW DESCRIPTION Test Access Port SARA-2 is a single-chip solution using feature/ application-specific microcode that performs complete segmentation and reassembly SAR for implementing

ALI-25

Abstract: multiplexing demultiplexing e2 e3 multiplexing e2 frame e3 strand demultiplexer standar LTE TS-501
Contextual Info: R TS-501 TECHNOLOGY SEMINAR Technology Seminar • Voice Networks Telephony • Data Networks (Datacom) Copyright c 1996 TranSwitch Corporation ALI-25, COBRA, CUBIT, CellBus and PHAME are trademarks of TranSwitch Corporation TranSwitch, TXC, SONGEN, XBERT, and SARA are registered trademarks of TranSwitch Corporation

IT16B

Contextual Info: CellBus ASPEN Device Access Processor TXC-05810B DATA SHEET DESCRIPTION • 155 Mbit/s bidirectional throughput • RISC-based hardware architecture • Dual independent CellBus interfaces for increased bandwidth or redundancy • UTOPIA Level 2P interface for cell and

Contextual Info: RF6559 RF65594.0V to 4.5V, 915MHz ISM BAND TRANSMIT/RECEIVE MODULE 4.0V TO 4.5V, 915MHZ ISM BAND TRANSMIT/RECEIVE MODULE 3 VCCD 4 GND RXC PAVCC2 2 GND TXC NC 1 DAVCC1 GND GND Package: LGA, 28-pin, 6mm x 6mm 28 27 26 25 24 23 22 GND 21 PDET 20 TXEN 19 RXEN

Contextual Info: SARA-2 ATM Cell Processing 1C Device TXC-05551 DATA SHEET PRODUCT PREVIEW DESCRIPTION FEATURES Full-duplex segmentation and reassembly of multiple VCs up to 155 Mbit/s in each direction Integrated SONET/SDH 155 Mbit/s framer Optional 8-bit UTOPIA interface

VIP 22A

Abstract: BC 4E7 ch341a 2048KHZ SS125 AMI 1108 ch3406
Contextual Info: QE1F Device Quad E1 Framer TXC-03104 DATA SHEET DESCRIPTION = • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode • Frame alignment detection and loss of frame

X32B

Abstract: 00BF sot 23
Contextual Info: BACK SARA-2 ATM Cell Processing IC Device TXC-05551 DATA SHEET PRODUCT PREVIEW DESCRIPTION • Functionality enabled by application-specific microcode e.g., SARA-Lite Microcode • Full-duplex segmentation and reassembly of multiple VCs up to 155 Mbit/s in each direction

ALI-25T

Abstract: SALI-25C TXC-07225-BCPL 82528 samsung LRA
Contextual Info: SALI-25C Device Six ATM Line Interface at 25 Mbit/s TXC-07625 DATA SHEET FEATURES DESCRIPTION • Transmission Convergence - meets ATM Forum specifications - maps ATM cells to six 25.6 Mbit/s payloads - NRZI/NRZ and 5B/4B conversions - scrambling, cell delineation and rate adaptation

AD29

Abstract: AD30 TXC-05551 RH -005c RELAY
Contextual Info: SARA-2 ATM Cell Processing IC Device TXC-05551 DATA SHEET PRODUCT PREVIEW DESCRIPTION • Functionality enabled by application-specific microcode e.g., SARA-Lite Microcode • Full-duplex segmentation and reassembly of multiple VCs up to 155 Mbit/s in each direction

ALI-25T

Abstract: SALI-25C TXC-07225-BCPL nec 07225
Contextual Info: SALI-25C Device Six ATM Line Interface at 25 Mbit/s TXC-07625 DATA SHEET DESCRIPTION FEATURES • Transmission Convergence - meets ATM Forum specifications - maps ATM cells to six 25.6 Mbit/s payloads - NRZI/NRZ and 5B/4B conversions - scrambling, cell delineation and rate adaptation

B15C

Abstract: d0415 TB-33 RB35
Contextual Info: HDLC Device HDLC Controller, 36-bit Terminal I/O TXC-05101 DATA SHEET Preliminary . FEATURES = = = = = ¿ ^ - 1 - -— DESCRIPTION = • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion • Operates up to 51.84 Mbit/s STS-1 data rates

1SA5

Abstract: byc 22d
Contextual Info: QE1F Device Quad E1 Framer TXC-03104 DATA SHEET FEATURES DESCRIPTION = • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode • Frame alignment detection and loss of frame

Contextual Info: tm ä nX-S w it c h „ SALI-25C Device Six ATM Line Interface at 25 Mbit/s TXC-07625 DATA SHEET FEATURES DESCRIPTION • Transmission Convergence - meets ATM Forum specifications - maps ATM cells to six 25.6 Mbit/s payloads - NRZI/NRZ and 5B/4B conversions

Contextual Info: „ tm ä n S w it c h SALI-25C Device Six ATM Line Interface at 25 Mbit/s TXC-07625 X- DATA SHEET DESCRIPTION FEATURES • Transmission Convergence - meets ATM Forum specifications - maps ATM cells to six 25.6 Mbit/s payloads - NRZI/NRZ and 5B/4B conversions