T0041S2 Search Results

Contextual Info: DJB Device Quad DS1 Dejitter Buffer TXC-03351 DATA SHEET Preliminary FEATURES = • = .■ : = • Reduces receive jitter on DS1 signals due to transmission and stuffing source jitter • Dejitters four DS1 signals • Satisfies Bellcore category I jitter requirements

566 pin diagram

Abstract: 734A coaxial cable hp54502a hp3784A TAIS SOT TXC-02021 power combiner broadband transformers HP-3784A 10A ferrite bead b3-z
Contextual Info: ART Devices Advanced DS3/STS-1 Receiver/Transmitter ART: TXC-02020 44-Pin ARTE: TXC-02021 (68-Pin) • Single device line interface for DS3 and STS-1 • Single +5V power supply • Meets ‘crossconnect frame’ mask requirements • Adaptive equalization for 0 - 450 ft. of cable

DAX 3S

Contextual Info: L3M Device Level 3 Mapper TXC-03452 DATA SHEET Product Preview i—— = = = = = = = = = = • SDH/SONET bus access: -Drop/add data byte access with clock, C1J1, SPE, and parity -Add bus interface timing derived from drop bus, add bus, or external timing

RD4A

Contextual Info: XBERT Device Bit Error Rate Generator Receiver TXC-06125 DATA SHEET Preliminary FEATURES = — — — - = • Serial, nibble, or byte wide interface capability • Transmit and receive clock rate: 100 Hz to 52.00 MHz serial, byte, nibble I/O (All telecom rates

LOS13

Abstract: DR24 motor T2X6
Contextual Info: M13E Device DS3/DS1 MUX/DEMUX, Extended Features TXC-03303 DATA SHEET Product Preview DESCRIPTION ". = • Multiplexes/demultiplexes 28 DS1 signals into a DS3 signal. = The M13E is a CMOS VLSI device with extended fea­ tures that provides the functions needed to multiplex

SARA-S

Abstract: vlsi TXC-05501 SYN155C TXC-02050 TXC-05601 sara-r TXC-99002-MC
Contextual Info: SARA-S and SARA-R Devices ATM/SMDS Segmentation Controller, TXC-05501 ATM/SMDS Reassembly Controller, TXC-05601 m/ibOu PRODUCT INFORMATION FEATURES DESCRIPTION • SARA-S Segmentation Controller TXC-05501 segments packets into ATM/SMDS cells, up to 8000

Contextual Info: COBRA Device Constant Bit Rate ATM Adaptation Layer 1 TXC-05427B DATA SHEET FEATURES = nFsrm PTinN — - = COBRA C onstant Bit Bate ATM Adaptation Layer 1 is a four-channel VLSI device that implements all of the functions needed for circuit emulation over ATM. Both

Contextual Info: QDS1F Device QUAD DS1 Framer TXC-03102 DATA SHEET Preliminary = • D4 SF, ESF including FDL support , and transparent framing modes DESCRIPTION m ssg.ss=saam .i i = • Detects, counts and forces line code errors (BPVs and excess zeros), CRC errors (ESF

Contextual Info: E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET PRODUCT PREVIEW = • Multiplexer/demultiplexer for ITU-T Recommendations: G.742 E2 frame format G.751 (E3 frame format) DESCRIPTION = The E123MUX is a CMOS VLSI device that provides the E13 functions needed to multiplex and demultiplex

Contextual Info: XBERT Device Bit Error Rate Generator Receiver TXC-06125 DATA SHEET FEATURES DESCRIPTION - = The Bit Error Rate Generator/Receiver XBERT VLSI device is a microprocessor-programmable multi-rate test pattern generator and receiver on a single chip. It is used for testing the performance of digital communica­

Contextual Info: JT2F Device 6 Mbit/s Framer TXC-03702 DATA SHEET FEATURES = DESCRIPTION • Framer for: - CCITT Recommendation G.704 - NTT-specified 6312 kbit/s format = The JT2 Framer JT2F is a CMOS VLSI device that provides the functions needed to frame a wideband payload to G.704 and the NTT-specified 6312 kbit/s

JD 1801 PIN DIAGRAM

Abstract: RTCO Z511A epoch t14 12D1C-D ET 723 TAIS SOT TA-NWT-000253 s004152 0Q0043
Contextual Info: SOT-1 Device SONET STS-1 Overhead Terminator TXC-03001 DATA SHEET Preliminary FEATURES DESCRIPTION Provides SONET interface to any type of payload = The SOT-1 SONET/STS-1 Overhead Terminator per­ forms section, line and path overhead processing for STS-1 SONET signals. This versatile device can be

0.1 micro farad capacitor

Contextual Info: SYN155 Device 155-Mbit/s Synchronizer, Data Output TXC-02301B DATA SHEET FEATURES .= DESCRIPTION = • Transmits and receives at S T S -3/S TM -1 rates The S Y N 1 55 synchronizer device provides a complete S T S -3 / STM -1 fram e synchronization function in a single low-power

TXC CXO

Abstract: QDD032D xck-t PBIT
Contextual Info: DS3F Device DS3 Framer TXC-03401 DATA SHEET FEATURES " ^ = = = = = ^ = = = = = = = -• DS3 payload access, bit-serial or nibble-parallel • C-bit parity or M13 operating mode • C-bit interface 13 C-bits in, 14 out • Detect and generate DS3 AIS, and idle signals

SYN155C

Abstract: TT 46 N 16 LOF f 8212 microprocessor 8212 block diagram
Contextual Info: SYN155C Device 155-Mbit/s Synchronizer Clock & Data Output TXC-02302B DATA SHEET FEATU RES. — . = DESCRIPTION:. = • T ransm its and receives at S T S -3 /S T M -1 rates T h e TranS w itch • C o m p atib le with a v a ila b le optical com po nen ts

Contextual Info: SOT-3 Device STM-1/STS-3/STS-3c Overhead Terminator TXC-03003B DATA SHEET Product Preview DESCRIPTION •.■■■= • Transport Section and Line Overhead byte processing • Independent Path Overhead byte processing • Transmit and receive pointer generation with