TTL AF Search Results
TTL AF Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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9317CDM |
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9317 - Decoder/Driver, TTL, CDIP16 |
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DM8131N |
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DM8131 - Identity Comparator, TTL, PDIP16 |
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74141PC |
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74141 - Display Driver, TTL, PDIP16 |
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MM54C901J/883 |
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54C901 - Hex Inverting TTL Buffer |
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MC529F/R |
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MC529 - Inverter, TTL, CDFP14 |
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TTL AF Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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CHARACTERIZATION
Abstract: GTLP6C816 GTLP6C816A curve
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GTLP6C816A MS500284 CHARACTERIZATION GTLP6C816 GTLP6C816A curve | |
Contextual Info: IDT74GTLP816 GTLP / TTL 1:2 / 1:6 CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE GTLP/TTL 1:2/1:6 CLOCK DRIVER FEATURES: • • • • • • • • DESCRIPTION: 5V or 3.3V operation Interface between GTLP and TTL logic levels GTLP to TTL 1:6 fanout TTL to GTLP 1:2 fanout |
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IDT74GTLP816 IDT74GTLP | |
XEL28
Abstract: marking k8 diode
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SY10ELT28 SY100ELT28 160MHz SY10/100ELT28 XEL28 marking k8 diode | |
Contextual Info: *SYNERGY PECL/TTL-TTL 1:8 CLOCK DISTRIBUTION CHIP SEMICONDUCTOR FEATURES Clockworks PRELIMINARY SY10/100H646 DESCRIPTION • PECL/TTL-TTL version of popular ECLinPS E111 ■ Meets specifications required to drive highperformance x86 processors ■ Guaranteed low skew specification |
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SY10/100H646 SY10H646 SY100H646 28-lead IVT01 -------300pF 200pF 100pF 0013fi | |
9434
Abstract: CY101E383 EME-6300H
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CY101E383 CY10E383 CY101E383-JC 9434 CY101E383 EME-6300H | |
IDT74GTLP816Contextual Info: IDT74GTLP816 GTLP / TTL 1:2 / 1:6 CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE GTLP/TTL 1:2/1:6 CLOCK DRIVER FEATURES: • • • • • • • DESCRIPTION: Interface between GTLP and TTL logic levels GTLP to TTL 1:6 fanout TTL to GTLP 1:2 fanout Edge Rate Control Circuit reduces output noise on GTLP port |
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IDT74GTLP816 IDT74GTLP IDT74GTLP816 | |
FMEM-TTL
Abstract: manchester encoder block diagram manchester code encoder diagram Engineered Components Company manchester encoder Manchester block diagram manchester Manchester code
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MIL-HDBK-217, 50VDC FMEM-TTL manchester encoder block diagram manchester code encoder diagram Engineered Components Company manchester encoder Manchester block diagram manchester Manchester code | |
HLT28
Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28
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MC10ELT28, MC100ELT28 HLT28 KLT28 MC10ELT28/D HLT28 HT28 KLT28 KT28 MC100ELT28 MC10ELT28 | |
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading |
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MC10ELT28, MC100ELT28 HLT28 KLT28 MC10ELT28/D | |
klt28
Abstract: MC10ELT28 HLT28
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MC10ELT28, MC100ELT28 MC10ELT/100ELT28 ELT28 MC100ELT28 AN1404 AN1405 AN1406 AN1503 klt28 MC10ELT28 HLT28 | |
KLT28
Abstract: kt28 HLT28 HT28 MC100ELT28 MC10ELT28
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MC10ELT28, MC100ELT28 MC10ELT/100ELT28 ELT28 MC10ELT28/D KLT28 kt28 HLT28 HT28 MC100ELT28 MC10ELT28 | |
max232 rts cts
Abstract: TTL-232R-3V3 cmos 3v3 TTL232R-3V3 FT232RQ FT232R USB UART ttl drive USB CABLE MAX232 for level converter notes on serial communication MAX232
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TTL-232R-3V3 TTL-232R-3V3 FT232RQ FT232R max232 rts cts cmos 3v3 TTL232R-3V3 FT232R USB UART ttl drive USB CABLE MAX232 for level converter notes on serial communication MAX232 | |
SY100H841
Abstract: SY100H841ZC SY10H841 SY10H841ZC SY10H841ZCTR
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SY10H841 SY100H841 300ps 500ps SY10/100H841 SY10H841ZC SY100H841 SY100H841ZC SY10H841 SY10H841ZC SY10H841ZCTR | |
Contextual Info: * SYNERGY LOW-POWER HEX TTL-TO-PECL TRANSLATOR SY100S391 SEMICONDUCTOR DESCRIPTION FEATURES Operates from a single +5V supply Differential PECL outputs The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique |
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SY100S391 SY100S391 | |
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fairchild ECL
Abstract: 75453btc 55450B 754S3B
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100324Contextual Info: Revised November 1999 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable |
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Contextual Info: IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER FEATURES: • • • • • DESCRIPTION: Bidirectional interface between GTLP and TTL logic levels Edge Rate Control Circuit reduces output noise |
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IDT74GTLP16612 18-BIT | |
GTLP16612
Abstract: IDT74GTLP16612
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IDT74GTLP16612 18-BIT GTLP16612 IDT74GTLP16612 | |
Contextual Info: * SYNERGY SEMICONDUCTOR SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise |
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300ps 500ps SY10H841 SY100H841 10/100H | |
100324PC
Abstract: 100324QC 100324QI 100324SC M24B MS-013 N24E V28A 100124 100324
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ELT24
Abstract: SY100ELT24 SY100ELT24ZC SY100ELT24ZCTR
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SY100ELT24 500ps SY100ELT24 ELT24 SY100ELT24ZC SY100ELT24ZCTR ELT24 SY100ELT24ZC SY100ELT24ZCTR | |
H604
Abstract: MC100H604 MC100H604FN MC10H604 MC10H604FN
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MC10H604, MC100H604 MC10H/100H604 r14525 MC10H604/D H604 MC100H604 MC100H604FN MC10H604 MC10H604FN | |
Contextual Info: * LOW-POWER HEX TTL-TO-PECL TRANSLATOR SYNERGY SY100S391 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this |
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SY100S391 SY100S391 SY100S391DC D24-1 SY100S391FC F24-1 SY100S391JC | |
A1610
Abstract: 100324
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