TQ013 Search Results

SY100E111

Abstract: SY10E111
Contextual Info: This Material Copyrighted By Its Respective Manufacturer * C lockw orks SY10E111 SY100E111 SYNE R G Y SEM IC O N D U C TO R B L O C K D IA G R A M D C E L E C T R IC A L C H A R A C T E R IS T IC S VEE = V ee Min. to V ee (M ax.); V c c = VCCO = G N D

DG7-32

Contextual Info: * SYNERGY DATA S E P A R A TO R PRELIMINARY SY10E197 SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ 2:7 and 1:7 RLL format-compatible Fully Integrated Vco for 50Mb/s operation External Vco input for higher operating frequency Anti-equivocation circuitry to ensure PLL lock

HP70004A

Abstract: HP53132A OV 5642 70874B
Contextual Info: * SONET/SDH/ATM OC-3 CLOCK RECOVERING TRANSCEIVER SYNERGY SEM IC O N D UC TO R FEATURES DESCRIPTION • A complete SONET/SDH Transmitter & Receiver ■ Complies with Bellcore, CCITT and ANSI Specifications ■ Two on-chip PLLs: One for clock generation & another for clock recovery

Contextual Info: * SINGLE SUPPLY QUAD PECL-TO-TTL WITH OUTPUT ENABLE SYNERGY SEMICONDUCTOR FEATURES ClockWorks SY10H841 SY100H841 DESCRIPTION • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

Contextual Info: * SYNERGY DUALTTL-to-DIFFERENTIAL PECLTRANSLATOR SY10ELT22 SY100ELT22 SEMICONDUCTOR DESCRIPTION FEATURES 300ps typical propagation delay <100ps typical output-to-output skew Differential PECL outputs PNP TTL inputs for minimal loading Flow-through pinouts

DDD1173

Abstract: SY100E131 SY10E131
Contextual Info: * SYNERGY S E M IC O N D U C T O R SY10E131 SY100E131 4-BIT D FLIP-FLOP FEATURES DESCRIPTION 1100MHz min. toggle frequency The SY10/100E131 are high-speed quad m aster slave D-type flip-flops with differential outputs designed for use in new, high-perform ance ECL system s. The flip -flop s may

F100K

Abstract: SY100S355 tia ,dna
Contextual Info: * SYNERGY QUAD m u l t ip l e x e r / l a t c h syioossbs S E M IC O N D U C T O R FEATURES DESCRIPTION I M a x. p ro p a g a tio n d e la y o f 1 100ps The SY100S355 offers four transparent latches with differential outputs and is designed for use in high­

Contextual Info: * ENHANCED DIFFERENTIAL RECEIVER SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 3.3V and 5V power supply options ■ 250ps propagation delay ■ Very high voltage gain vs. standard EL16 ■ Ideal for Pulse A m plifier and Lim iting Am plifier applications

Contextual Info: * QUAD MULTIPLEXER/LATCH SYNERGY SY100S355 S E M IC O N D U C T O R FEATURES DESCRIPTION • Max. propagation delay of 110Ops ■ Max. enable to output delay of 1400ps ■ I e e min. of -80m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels

F100K

Abstract: SY100S336
Contextual Info: * 4-STAGE COUNTER/ SHIFT REGISTER SYNERGY S EM IC O N D U C TO R FEATURES D E S C R IP T IO N I l I I I I I Max. shift frequency of 700MHz Clock to Q delay max. of 1lOOps lE E m ln . of -170mA ESD protection of 2000V Internal 75KÎ2 input pull-down resistors

E151

Abstract: SY100EL51ZC SY10EL51 SY10EL51ZC flip-flop 555
Contextual Info: *SYNERGY PRELIMINARY SY10EL51 SY100EL51 DIFFERENTIAL CLOCK D FLIP-FLOP SEMICONDUCTOR FEATURES_ • DESCRIPTION ■ 475ps propagation delay ■ 2.8GHz toggle frequency The SY10EL/100EL51 are differential clock D flip-flops with reset. These devices are functionally sim ilar to the

Contextual Info: * SYNERGY SEMICONDUCTOR 125 MHz DIGITALLY PROGRAMMABLE TIMING EDGE VERNIER PRELIMINARY SY69605 DESCRIPTION FEATURES • True 125MHz retrlgger rate ■ Pin-compatible with Bt605 ■ I5ps delay resolution ■ Less than ± 1 LSB timing accuracy ■ Differential TRIGGER and delay WRITE inputs