TG013 Search Results

Contextual Info: * ULTRA-HIGH-SPEED 64-WORD x 18-BIT FIFO SYNERGY SY69168 SEMICONDUCTOR FEATURES DESCRIPTION • 10ns read and/or write cycle ■ System clock speeds to 100MHz ■ Selectable OVERFLOW and UNDERFLOW interrupts ■ EMPTY, FULL and HALF-FULL status flag outputs

QY10

Abstract: F100K SY100S302 SY100S302DC
Contextual Info: « Q U IN T 2 -IN P U T O R /N O R G A T E SYNERGY Q vinosso? SY1Û0S302 S E M IC O N D U C T O R DESCRIPTION FEATURES The S Y 100S 302 offers five 2 -in p u t O R/N O R gates designed fo r use in high-perform ance ECL system s. The five gates are controlled by a com m on Enable signal. All

"Parity Checker"

Abstract: F100K SY100S360 SY100S360DC SY100S360FC
Contextual Info: « DUAL PARITY CHECKER/GENERATOR SYNERGY SEMICONDUCTOR FEATURES SY100S360 D E S C R IP T IO N • Max. propagation delay of 2200ps ■ I ee min. of -70mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option:

SY100EL89ZC

Abstract: SY10EL89 SY10EL89ZC
Contextual Info: * COAXIAL CABLE DRIVER SYNERGY S EM IC O N D U C TO R FEATURES DESCRIPTION 375ps propagation delay 1-6V output swings The SY10EL89 is a differential fanout gate specifically designed to drive coaxial cables. The device is especially useful in Digital Video Broadcast applications. For this

Contextual Info: * FEATURES_ • ■ ■ ■ 700ps max. propagation delay Differential outputs ESD protection of 2000V Fully compatible with Industry standard 10KH, 100K ECL levels ■ Extended 100E Vee range of -4.2V to -5.46V ■ Internal 75Kil input pulldown resistors

Contextual Info: V 4- b it s e r ia l / p a r a l l e l CONVERTER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • On-chip clock +4 and -Hi ■ 2.5Gb/s data rate capability ■ Differential clock and serial Inputs ■ V bb output for single-ended use ■ ■ ■ ■ ■ ■

Contextual Info: * 6-BIT 2:1 MUX-LATCH SYNERGY SY10E155 SY100E155 SEMICONDUCTOR FEATURES DESCRIPTION • ■ ■ ■ ■ ■ ■ 750ps max. LEN to output 700ps max. D to output Single-ended outputs Asynchronous Master Reset Dual latch-enables ESD protection of 2000V Fully compatible with industry standard 10KH,

TO220V

Contextual Info: « 5-BIT REGISTERED TRANSCEIVER SYNERGY SY100S891 SEMICONDUCTOR FEATURES DESCRIPTION 25 ohm cut-off bus outputs 50 ohm receiver outputs Transm it and receive registers w ith separate clocks 1500ps max. delay from C LKi to Bus O utputs BUS 1500ps max. delay from CLK 2 to Receiver O utputs

EL34

Abstract: 10el34 100EL34
Contextual Info: * Clockworks 5V/3.3V - 2 , -4 , - 8 CLOCK GENERATION CHIP SYNERGY SY10EL34/L SY100EL34/L SEMICONDUCTOR FEATURES DESCRIPTION 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KQ input pull-down resistors

SY100E116

Abstract: SY10E116 SY10E116JC
Contextual Info: * QUINT DIFFERENTIAL LINE RECEIVER SYNERGY S E M IC O N D U C T O R FEATURES DESCRIPTION I 45 0 p s m ax. P ro p a g a tio n D elay The S Y 1 0/1 0 0 E 1 16 are quint differential line receivers designed for use In new, high-perform ance ECL system s. T hese device s have e m itte r-fo llo w e r o u tp u ts and an

SY100ELT22

Abstract: 100ELT22 ELT22 SY10ELT22 100EL22 10el2
Contextual Info: « DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR SYNERGY S E M IC O N D U C T O R F EA TU R E S D ES C R IPTIO N 300ps typical propagation delay <100ps typical output-to-output skew Differential PECL outputs The SY10/100ELT22 are dual TTL-to-differential PECL translators. Because PECL Positive ECL levels are

sy89429jc

Abstract: "Z3N" SY89429
Contextual Info: SYNERGY Clockworks PRELIMINARY SY89429 FREQUENCY SYNTHESIZER SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ 25 to 400MHz differential PECL outputs ±25ps output jitter within 100 cycles Minimal frequency over-shoot Synthesized architecture Serial 3 wire interface

Contextual Info: SYNERGY * SEMI CONDUCTOR SYNERGY SEMICONDUCTOR S7E D • «ìGOiafil b3T ■ SY10L494-7/8/10 SY100L494-7/8/10 SY 101L494-7/8/10 LOW POWER 16K x 4 ECL RAM FEATURES OGQOOaa DESCRIPTION ■ Address access time, tAA: 7/8/1 Ons max. ■ Chip select access time, tAc: 3/4/5ns max.

Contextual Info: * TRIPLE 5-INPUT OR/NOR GATE SYNERGY Qv-mn^m SY100S301 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 750ps I e e min. of-25mA ESD protection of 2000V Industry standard 100K ECL levels Extended supply voltage option: — VEE = -4.2V to-5.46V

Allen-Bradley 100-M09

Abstract: 100-C09D10 KRY 112 71/2 193-EF1A Allen-Bradley 100-c09*10 193-EF2A 193-EF 140M-C2E-C10 Allen-Bradley 100-c09D10 140M-C-AFA11
Contextual Info: Bulletin 100 Line IEC Contactors, Starters, and Overload Relays Section Overview Motor Protection Circuit Breakers • Bulletin 140M Motor Protection Circuit Breakers Page 5 • Bulletin 140M Motor Circuit Protectors Page 7 • Bulletin 140M Accessories

Contextual Info: * 16-INPUT MULTIPLEXER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION The SY100S364 is a 16-input multiplexer designed for use in high-performance ECL systems. The four Data Select inputs So, S i, S 2, S3 determine the bit from the 16 inputs (in ) that will be passed on to the output as shown in the Truth

Contextual Info: « SINGLE SUPPLY QUAD PECL-TO-TTL WITH OUTPUT ENABLE SYNERGY SEMICONDUCTOR Clockworks SY10H841 SY100H841 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

E137

Abstract: SY100E137 SY10E137 SY10E137JC 100E137
Contextual Info: * 8 ' B IT R IP P L E SYNERGY S E M IC O N D U C TO R COUNTER FEATURES DESCRIPTION 1.8GHz m in. c o u n t fre q u e n c y E xtended 100E V ee range o f -4 .2 V to -5 .5 V S y n c h ro n o u s and a s y n c h ro n o u s e nable pin s D iffe re n tia l c lo c k in p u t and data o u tp u t p in s

Contextual Info: * OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER SYNER G Y SEMICONDUCTOR .NFORMATON SY69951 DESCRIPTION FEATURES • SONET/SDH and ATM Compatible ■ Seamless operation with PMOSierra PM5345 SUNI, VTIVNS67200 Quad UNI Processor, IgT WAC-013-B ATM UNI Processor and NEC ^tPD98402