10EL34 Search Results

Contextual Info: * C lo c k w o rk s 10EL34/L SY100EL34/L 5V/3.3V +2, +4, ^8 CLOCK GENERATION CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION 3.3V and 5V power supply options 50ps ou tput-to-output skew Synchronous enable/disable Master Reset fo r synchronization Internal 75KQ input pull-down resistors

E142 wafer format

Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Contextual Info: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved”

100EL34G

Abstract: el34 MR 4010 MC100EL34 MC10EL34
Contextual Info: 10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

Contextual Info: 10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

Contextual Info: 10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

KLT20

Abstract: k1648 klt22 KEL32 MC100 HEP64 KLT21 LP17 KEP32 HEP139
Contextual Info: AND8002/D ECLinPS, ECLinPS Lite, ECLinPS Plus, ECLinPS MAX, and GigaComm Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and

kvt22

Abstract: KVL11 KPT23 ON Semiconductor marking k1648 KLT20 HEL16 KEL32 KEL01 xaa9646
Contextual Info: AND8002/D ECLinPS, ECLinPS Lite and ECLinPS Plus Device Type and Date Code Marking Guide Gary Richards, ECL Logic Product Engineering http://onsemi.com APPLICATION NOTE need ON Semiconductor’s marking spec 12MON00232D and S.O.P. 7–19 ID of Products to Location of

Contextual Info: 10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

EL34

Abstract: 10el34 100EL34
Contextual Info: * Clockworks 5V/3.3V - 2 , -4 , - 8 CLOCK GENERATION CHIP SYNERGY 10EL34/L SY100EL34/L SEMICONDUCTOR FEATURES DESCRIPTION 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KQ input pull-down resistors

100EL34

Abstract: el34 EL34 circuit EL34 single ended 10EL34 SY10EL34LZC
Contextual Info: ClockWorks 10EL34/L SY100EL34/L FINAL 5V/3.3V ÷2, ÷4, ÷8 CLOCK GENERATION CHIP FEATURES • ■ ■ ■ ■ DESCRIPTION The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are

EL34

Abstract: 100EL34 10EL34 EL34 circuit SY10EL34LZC
Contextual Info: 5V/3.3V ÷2, ÷4, ÷8 CLOCK GENERATION CHIP FEATURES • ■ ■ ■ ■ DESCRIPTION The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output

Contextual Info: * 5V/3.3V - 2 , *4 , ^ SYNERGY CLOCK GENERATION CHIP SY100EL34/L SEMICONDUCTOR FEATURES DESCRIPTION 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K£2 input pull-down resistors

EL34

Abstract: SY100EL34LZC SY100EL34LZCTR SY10EL34LZC SY10EL34LZCTR SY10EL34LZI SY100EL34LZG TR 100EL34
Contextual Info: 5V/3.3V ÷2, ÷4, ÷8 CLOCK GENERATION CHIP Micrel, Inc. Precision Edge 10EL34/L Precision Edge® SY100EL34/L 10EL34/L SY100EL34/L FEATURES • ■ ■ ■ ■ 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization

Contextual Info: Clockworks 10EL34/L SY100EL34/L 5V/3.3V +2, -4 , - 8 CLOCK GENERATION CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION 3.3 V an d 5V p o w e r s u p p ly o p tio n s T h e S Y 1 0 /1 0 0 E L 3 4 /L a re lo w s k e w -h2, -¡-4, -^8 c lo c k g e n e ra tio n c h ip s d e s ig n e d e x p lic itly fo r lo w s k e w c lo c k

mr 4020

Abstract: el34 MC100EL34 MC10EL34 10EL34G hl 4020 100EL34G
Contextual Info: 10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

Contextual Info: ^ 5V/3.3V -2 , -4 , - 8 CLOCK GENERATION CHIP SYNERG Y C SY100EL34/L SEMICONDUCTOR DESCRIPTION FEATURES • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization ■ Internal 75KÌ2 input pull-down resistors

Contextual Info: ^ 5V/3.3V -2 , -4 , - 8 CLOCK GENERATION CHIP SYNERG Y C SY100EL34/L SEMICONDUCTOR DESCRIPTION FEATURES • 3.3V and 5V power supply options ■ 50ps output-to-output skew ■ Synchronous enable/disable ■ Master Reset for synchronization ■ Internal 75KÌ2 input pull-down resistors

MR 4010

Abstract: el34 100EL34 10EL34 MC100EL34 MC100EL34D MC100EL34DR2 MC10EL34 MC10EL34D MC10EL34DR2
Contextual Info: 10EL34, MC100EL34 5VĄECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

SY100EL34zg

Contextual Info: 10EL34/L SY100EL34/L 5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip Precision Edge General Description The SY10/100EL34/L are low-skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low-skew clock generation applications. The internal dividers are

HEL16

Abstract: DEVICE MARKING CODE table onsemi marking marking code onsemi marking code onsemi Diode kel33 on semiconductor traceability marking soic HEL32 HEL12 HEL31 HEL05
Contextual Info: AND8002/D ECLinPS, ECLinPS Lite, ECLinPS Plus, ECLinPS MAX, and GigaComm Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and

Contextual Info: * SYNERGY Clockworks 10EL34/L SY100EL34/L 5V/3.3V -h2, -h4, -h8 CLO CK G ENERATIO N CHIP SEMICONDUCTOR DESCRIPTION FEATURES 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KÌ2 input pull-down resistors

Contextual Info: * Clockworks 10EL34/L SY100EL34/L 5V/3.3V ^2, - 4 . - 8 CLOCK GENERATION CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable M aster Reset for synchronization Internal 75K£i input pull-down resistors

el34

Abstract: 100EL34 10EL34 MC100EL34 MC100EL34D MC100EL34DR2 MC10EL34 MC10EL34D MC10EL34DR2
Contextual Info: 10EL34, MC100EL34 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common

el34

Abstract: EL34 single ended
Contextual Info: 5V/3.3V ÷2, ÷4, ÷8 CLOCK GENERATION CHIP Precision Edge 10EL34/L SY100EL34/L FINAL FEATURES • ■ ■ ■ ■ 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input pull-down resistors