TP2640ND Search Results

VP1304N2

Abstract: TP2540ND VN1304N3 VP3203N3 LND150N8 VN3205N5 VN1310N3 TN2510N8 TN0102N2 VP1306N2
Contextual Info: _ _ fflpSupertex inc. Device Page # Device Page # Device A lp h a n u m e ric Index Page # Device Page# 2N7002 BSS123 DN2535N2 DN2535N3 DN2535N5 20 24 28 28 28 TN2106K1 TN2106N3 TN2124K1 TN2501N8 TN2501ND 57 57 61 63 63 TP2504ND TP2506ND TP2510N8 TP2510ND

Contextual Info: TP2635 TP2640 Supertex inc. Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package b v dss/ R d S ON ^ G S (th ) ' d (ON) B V dgs (max) (max) (min) SO-8 TO-92 Diet -350V i5 n -2.0V -0.7A - TP2635N3 TP2635ND

A773* Transistor

Abstract: TP2635 TP2635LG TP2635N3 TP2635ND TP2640 TP2640LG TP2640N3 TP2640ND A773
Contextual Info: TP2635 TP2640 Supertex inc. Low Threshold Preliminary P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package b v dss/ ^DS ON b v dgs (max) (max) (min) SO-8 TO-92 DICEt -350V 15£2 -2.0V 0.7A TP2635LG TP2635N3 TP2635ND -400V

P2640

Abstract: 125OC TP2640 TP2640ND TP2640LG-G to92 fet p channel
Contextual Info: TP2640 P- Channel Enhancement-Mode Vertical DMOS FET Features ► ► ► ► ► ► ► General Description This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

Contextual Info: TP2640 P- Channel Enhancement-Mode Vertical DMOS FET Features ► ► ► ► ► ► ► ► General Description This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

TP2635

Abstract: TP2635N3 TP2640 TP2640LG TP2640N3 TP2640ND
Contextual Info: TP2635 TP2640 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information † Order Number / Package BVDSS / BVDGS RDS ON (max) VGS(th) (max) ID(ON) (min) SO-8 TO-92 Die† -350V 15Ω -2.0V -0.7A – TP2635N3 — -400V 15Ω -2.0V -0.7A

Contextual Info: TP2635 TP2640 S u p e rte x inc. Low Thresh old Preliminary P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information R ds on BVdgs (max) (max) -350V 15Q -2.0V -400V 15Q -2.0V Order Number / Package !f b v dss / SO-8 TO-92 DICE* 0.7A TP2635LG TP2635N3

7A, 100v fast recovery diode

Abstract: TP2635 TP2635N3 TP2635ND TP2640 TP2640LG TP2640N3 TP2640ND
Contextual Info: TP2635/TP2640 TP2635 TP2640 Low Threshold Preliminary P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information † Order Number / Package BVDSS / BVDGS RDS ON (max) VGS(th) (max) ID(ON) (min) SO-8 TO-92 DICE† -350V 15Ω -2.0V -0.7A – TP2635N3

Contextual Info: TP2635 TP2640 I_0W Threshold S iM fM C rtG X in c . P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Num ber / Package BVDSS / ^DS ON ^GS(th) ^D(ON) b v dgs (max) (max) (min) SO-8 TO-92 Diet -350V 15& -2.0V -0.7A - TP2635N3 — -400V

Contextual Info: TP2640 P- Channel Enhancement-Mode Vertical DMOS FET Features ► ► ► ► ► ► ► General Description This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

a1026

Abstract: TP2640N3-G
Contextual Info: TP2640 P- Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

TP2635

Abstract: TP2635N3 TP2640 TP2640LG TP2640N3 TP2640ND
Contextual Info: TP2635 TP2640 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information † Order Number / Package BVDSS / BVDGS RDS ON (max) VGS(th) (max) ID(ON) (min) SO-8 TO-92 Die† -350V 15Ω -2.0V -0.7A – TP2635N3 — -400V 15Ω -2.0V -0.7A

TP2635

Abstract: TP2635N3 TP2635ND TP2640 TP2640LG TP2640N3 TP2640ND
Contextual Info: TP2635 TP2640 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information † Order Number / Package BVDSS / BVDGS RDS ON (max) VGS(th) (max) ID(ON) (min) SO-8 TO-92 Die† -350V 15Ω -2.0V -0.7A – TP2635N3 TP2635ND -400V 15Ω -2.0V

Contextual Info: Prelim inary P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package b v dss/ ^DS ON ^GS(th) I d (ON) BVdgs (max) (max) (min) SO-8 TO-92 DICE+ -350V 15Q -2.0 V -0.7A - TP2635N3 TP2635ND -400V 15Q -2.0 V -0.7A TP2640LG TP2640N3

SW7 357

Abstract: HV803 ausi die attach CSI 2702 HV208 HV82 38495 VF01 VP03 AF03
Contextual Info: Chapter 19 – Die Specifications DMOS Die Specifications Selector Guide VF01/VF06/VF21/VF25 VF22/LND1/LP07 VF05/VF13/VF26/TN07 VF32/LNE1/LP08 AF03 LR6 LR7 HT04 HV15/HV16/HV18 HV202 HV204/HV217/HV218/HV227/HV228 HV207 HV208 HV209 HV21/HV22 HV31/49 HV34 HV45/HV46