TI007 Search Results

54ACT11373

Contextual Info: 54ACT11373, 74ACT11373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0079— 0 2 9 5 7 , JUNE 1987— REVISED MARCH 1990 54ACT11373 . . . JT PACKAGE 74ACT11373 . . . DW OH NT PACKAGE Inputs are TTL-Voltage Compatible 8 Latches in a Single Package

Arcol wirewound resistor

Abstract: TI002 Arcol HS50 NHS300 HS75 1K F hs50 100 1 TI005 TI006 HS300 ARCOL 19K36
Contextual Info: HEATSINK RANGE TECHNICAL INFORMATION LAST REVISED 01 NOV 2001 CONTENTS Critical Resistance TI002 Critical Resistance TI005 Critical Voltage TI002 Definition of Terms TI005 Derating Curve HS TI007 Electromagnetic Compatibility (EMC) TI009 Heatsink Selection

54AC11244

Abstract: ac11244 74AC 74AC11244 162A3
Contextual Info: 54AC11244, 74AC11244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0074— D3411, MAY 1987— REVISED MARCH 1990 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers S 4A C 11244 . . . J T P ACKA G E 7 4A C 11 2 44 . . . D W O R N T P A C K A G E

74ACT11245

Abstract: D2957
Contextual Info: 54ACT 11245, 74ACT11245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0077— D2957, JULY 1987— REVISED MARCH 1990 54ACT11245 IT PACKAGE 74ACT11245 . . . DW OR NT PACKAGE Inputs are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines Directly TOP VIEW

Contextual Info: 54ACT11244, 74ACT11244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0075— D2957, AUGUST 1967—REVISED MARCH 19 54ACT11244 . . . JT PACKAGE 74ACT11244 . . . DW OR NT PACKAGE Inputs are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer

Contextual Info: 54ACT11240, 74ACT11240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0072— D3410, M AY 1987— R E V IS E D M A R C H 1990 54ACT11240 . . . JT P A C K A G E 74ACT11240 . DW O R NT P A C K A G E • Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PC B

Contextual Info: 31E D TEXAS INSTR LOGIC a^biTE a D Q flaam 1 • m 54AC11373, 74AC11373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0078—02957, MAY 1997—REVISED MARCH 1990 8 Latches In a Single Package 54AC11373 . . . JT PACKAGE 74AC11373 . . . DW OR NT PACKAGE

54ACT11244

Abstract: act11241 74ACT11244 D2957
Contextual Info: 54ACT11244, 74ACT11244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0075— D2957, AUG UST 1987— REVhSED M ARCH 1990 54ACT11244 . . . JT PACKAGE 74ACT11244 . . . DW OR NT PACKAGE Inputs are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer

AC11373

Abstract: 74AC11373 D2957
Contextual Info: 54AC11373, 74AC11373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0078—D2957, MAY 1987—REVISED MARCH 1990 8 Latches in a Single Package 54AC 11373 . . . JT PAC KAG E 7 4A C 1 1 3 7 3 . . . D W O R N T P A C K A G E 3-State Bus-Driving True Outputs

54AC11245

Abstract: 74AC 74AC11245 D2957 TI0076
Contextual Info: 54AC11245, 74AC11245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0076— D2957, JULY 1987— REVISED MARCH 1990 3-State Outputs Drive Bus Lines Directly 54A C 11 2 45 IT P ACKA G E 7 4A C 11 2 45 . . . DW O R N T P ACKA G E Flow-Through Architecture to Optimize PCB

1Y3C

Abstract: 54AC11241 74AC11241 D2957
Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0071— D2957, JULY 1987— REVISED MARCH 1990 54AC11241 . . . JT PACKAGE 74AC11241 . . . DW OR NT PACKAGE 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers TOP VIEW

ACT11244

Abstract: 54ACT11241 74ACT11241 D2957
Contextual Info: 54ACT11241, 74ACT11241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0073— D2957, JU LY 1987— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54ACT11241 . . . JT PACKAGE 74ACT11241 . . . DW OR NT PACKAGE • 3-State Outputs Drive Bus Lines or Buffer

TT007

Contextual Info: 54AC11373, 74AC11373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0078— D2957, MAY 1987—REVISED MARCH 1990 8 Latches in a Single Package 54AC11373 . . . JT PACKAGE 74AC11373 . . . DW OR NT PACKAGE 3-State Bus-Driving True Outputs TOP VIEW

54AC11373

Abstract: B175D 10J2 74AC11373 AC11373 D2957
Contextual Info: TE X A S INSTR 31E D LOGIC Bi 6 T b l 7 E 3 QOflflflm 1 • T I I 3 S4AC11373, 74AC11373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0078—D2957, MAY 1907— REVISED MARCH 1990 • 8 Latches In a Single Package 54AC11373 . . . J T PACKAGE 74A C11373 . . . DW OR N T PACKAGE

act11373

Abstract: 54ACT11373 74ACT11373 D2957
Contextual Info: 54ACT11373, 74ACT11373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0079— 0 2 9 5 7 , JU N E 1987— REVISED M ARCH 1990 Inputs are TTL-Voltage Compatible S4ACT11373 . . . JT PACKAGE 74ACT11373 . . . DW OR MT PACKAGE 8 Latches in a Single Package

Contextual Info: 54AC11240, 74AC11240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0070—03408. MAY 1987—REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11240 . . . JT PACKAGE 74AC11240 . . . DW OR NT PACKAGE TOP VIEW • Center-PIn Vcc and GND Configurations to

D3411

Contextual Info: 54AC11244, 74AC11244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0074— 0 3 4 1 1 , M AY 1987— REVISED MARCH 19 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 54A C 11 2 44 . . . J T P A C K A G E 74A C 11 2 44 . . . D W O R N T P ACKA G E

Contextual Info: TEXAS XNSTR LOGIC 31E D m 6 ^ 1 7 2 3 0063741 3 M T I I 3 54ACT11240, 74ACT1124Q OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T ' 5 2 ' 0 7 - 0 TI0072— D3410, M AY 1987— REVISED MARCH 1990 Inputs are TTL-Voltage Compatible 54AC T11240 . . . J T PACKAGE

A354A

Contextual Info: M A rT 1 1 9 d S T d A r T U Íd 1? OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0077— D 2957, JULY 1987— REVISED MARCH 1990 Inputs are TTL-Voltage Compatible 5 4 A C T 1 1245 . . . JT P ACKA G E 7 4 A C T 1 1245 . . . D W OR N T PACKA GE 3-State Outputs Drive Bus Lines Directly

en18a

Contextual Info: 54AC11245, 74AC11245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0076— D2957, JULY 1987— REVISED MARCH 1990 54AC11245 . . . JT PACKAGE 74AC11245 . . . DW OR NT PACKAGE • 3-State Outputs Drive Bu s Lines Directly • Flow-Through Architecture to Optimize PC B

1990- 2335

Abstract: 74ACT11240
Contextual Info: TEXAS XNSTR LOGIC 31E D 6^1723 DOfiSTm fl M T I I 3 54ACT11240, 74ACT1124Q OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS - 5 T '¿ - 0 7 - 0 TI0072—D3410, MAY 1987—REVISED MARCH 1990 54ACT11240 . . . JT PACKAGE 74ACT11240 . . . DW OR NT PACKAGE

2AL-17

Abstract: 74AC11240
Contextual Info: 54AC11240, 74AC11240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0070— D3409, MAY 1987— REVISED MARCH 1890 Flow-Through Architecture to Optimize PCB Layout 54AC11240 . . . JT PACKAGE 74AC11240 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V cc and GND Configurations to

Contextual Info: 54ACT11241, 74ACT11241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T I0073— D2957 JULY 1987— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54A C T 11241 . . . J T P ACKA G E 74A C T11 2 41 . . . D W OH N T P ACKA G E • 3-State Outputs Drive Bus Lines or Buffer

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T I0071— D2957, JULY 19B7— REVISED MARCH 1990 54AC11241 . . . JT PACKAGE 74AC11241 . . . DW OR NT PACKAGE 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers TOP VIEW