S5S303 Search Results

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

74ACT16823

Abstract: D3955
Contextual Info: 74ACT16823 18-BIT BUS INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS16Q-D3955. APRIL 1991 -R EV IS ED APRIL 1993 * Member of the Texas Instruments Wldebus Family ' Packaged In Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Pin Spacings

SN751177

Abstract: 11A1 RS-422-A SN751177NSLE SN751178 QDT1114 D3381
Contextual Info: 1%11„ SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS _ S L L S 0 5 9 A - D3381, FEBRUARY 1 9 9 0 -R E V IS E D JANUARY 1993 Meets EIA Standards RS-422-A, RS485 SN751177 — N PACKAGE TOP VIEW Meets CCITT Recommendations V.10, V 11 X.26, X.27

Contextual Info: SN54ALS244B, SN54AS244, SN74ALS244C, SN74AS244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDAS142A- JULY 1907 - REVISED JULY 1994 3-State Outputs Orlvs Bus Unes or Buffer Memory Address Registers PNP Inputs Reduce DC Loading SN54ALS244B, SNS4AS244. . . J PACKAGE

Contextual Info: 74AC11646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS _ D2957, JULY 1987 - REVISED APRIL 1993 • I I V I * Independent Registers for A and B Buses * Multiplexed Real-Time and Stored Data * Flow-Through Architecture Optimizes

Contextual Info: 31E D TEXAS INSTR LOGIC a^biTE a D Q flaam 1 • m 54AC11373, 74AC11373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0078—02957, MAY 1997—REVISED MARCH 1990 8 Latches In a Single Package 54AC11373 . . . JT PACKAGE 74AC11373 . . . DW OR NT PACKAGE

Contextual Info: SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS _ SCLS191B - FEBRUARY 1993 - R EVISED APRIL 1996 • E P IC Enhanced-Performance Implanted CMOS • • • • • 2-(X SN54LV164. j or w package . .^db.orpw package

Contextual Info: 54ACT11109,74ACT11109 DUALJ-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, FEBRUARY 1987 - REVISED APRIL 1993_ logic symbol* 1Q 1Q 2Q 2Q t This symbol is In accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

D4060

Abstract: RS-422-A SN75ALS181 SN75ALS181NSLE
Contextual Info: SN75ALS181 DIFFERENTIAL DRIVER AND RECEIVER PAIR SLLS152 - D4060, DECEMBER 1992 Meets EIA Standards RS-422-A, RS-485, and CCITT Recommendations V.11 and X.27 N OR N S t PACKAGE TOP VIEW Low Supply Current Requirements 30 mA Max NC [ 1 R[ 2 RE[ 3 DE [ 4 D[ 5

74ACT16544

Abstract: D3649 lebao 2C87
Contextual Info: 74ACT16544 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS161 - D3649, AUGUST 1990 - REVISED APRIL 1993 • Member of the Texas Instruments WidebusT" Family » Packaged In Plastic 300-Mil Shrink Small-Outline Package Using 25-Mil Center-to-Center Pin Spacings

SN74AS806

Contextual Info: SN54ALS805A, SN54AS805B, SN74ALS805A, SN74AS805B HEX 2-INPUT NOR DRIVERS SQAS023C - DECEMBER 1982 - REVISED JANUARY 1998 • High Capacltlve-Drlve Capability • ALS805A Has Typical Delay Time of 4.2 ns Cl s 50 pF and Typical Power Dissipation of 4.2 mW Per Gate

Contextual Info: 54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SC AS050A- D3266, JANUARY 1989 - REVISED APRIL 1993 • I I • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems I I * incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception