TI009 Search Results

Arcol wirewound resistor

Abstract: TI002 Arcol HS50 NHS300 HS75 1K F hs50 100 1 TI005 TI006 HS300 ARCOL 19K36
Contextual Info: HEATSINK RANGE TECHNICAL INFORMATION LAST REVISED 01 NOV 2001 CONTENTS Critical Resistance TI002 Critical Resistance TI005 Critical Voltage TI002 Definition of Terms TI005 Derating Curve HS TI007 Electromagnetic Compatibility (EMC) TI009 Heatsink Selection

UTC 494 equivalent

Abstract: 74AC11520 D2957
Contextual Info: TEXAS INSTR LOGIC 31E D H 6^1753 □DflflflfiB h • TII3 54A C11520, 74A C11520 8-BIT IDENTITY C O M PA R A TO R S - t - i s - n - o o TI0099— D2957, JULY 1987—REVISED JANUARY 1990 • Compares Two 8-Bit Words 54AC11520 . . . J PACKAGE 74AC1152Q . . . DW OR N PACKAGE

54AC11643

Abstract: 74AC11643 74AC D2957
Contextual Info: 54AC11643, 74AC11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0095— D2957, JULY 1987— REVISED MARCH 1990 5 4A C 1 1 6 4 3 . . . J T P A C K A G E 74A C 1 1 6 4 3 . . . D W O fl N T P A C K A G E Flow-Through Architecture to Optimize PCB Layout TO P V IE W

54AC11623

Abstract: 74AC11623 74AC
Contextual Info: 54AC11623, 74AC11623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0091— D2957, JU LY 1987— REVISED MARCH 1990 5 4A C 11 6 23 . . . J T P ACKA G E 7 4 A C 11623 . . . D W O R N T P A C K A G E Local Bus-Latch Capability Flow-Through Architecture to Optimize PCB

74AC11623

Abstract: ba1324
Contextual Info: 54AC11623, 74AC11623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0091— D2957, JULY 1987— REVISED MARCH 1990 Local Bus-Latch Capability 54AC 11623 . . . J T P ACKA G E 74A C 11 6 23 . . . D W OR N T PACKA GE Flow-Through Architecture to Optimize PCB Layout

Contextual Info: 54AC11646, 74AC11646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS TI0097— 0 2 9 5 7 , JULY 1987— REVISED MARCH 1990 54AC11646 . . . JT PACKAGE 74AC11646 . . . DW OR NW PACKAGE • Independent Registers for A and B Buses • Multiplexed Real-Time and Stored Data

Contextual Info: 54ACT11640, 74ACT11640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0094— D2957, JULY 19B7— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54ACT11640 . . JT PACKAGE 74ACT11640 . . . DW OR NT PACKAGE Flow-Through Architecture to Optimize PCB

74ACT11620

Contextual Info: 54ACT11620, 74ACT11620 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0090— D2957, JULY 1987— REVISED MARCH 1990 Inputs are TTL-Voltage Compatible 54ACT11620 . . . JT PACKAGE 74ACT11620 . . . DW OB NT PACKAGE Local Bus-Latch Capability TOP VIEW Flow-Through Architecture to Optimize PCB

Contextual Info: 54AC11520, 74AC11520 8-BIT IDENTITY COMPARATORS TI0099— D2957, JULY 1987— REVISED JANUARY 1990 • Compares Two B-BIt Words 5 4 A C 11520 . . . J P ACKA G E 74A C 11 5 20 . . . D W OR N P A C K A G E Flow-Through Architecture to Optimize PCB Layout • EPIC Enhanced-Performance Implanted

Contextual Info: 54ACT11646, 74ACT11646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS TI0098— 0 2 9 5 7 . JULY 1987— REVISED MARCH 1990 54ACT11646 . . . JT PACKAGE 74ACT11646 . . . DW OR NT PACKAGE • Inputs are TTL-Voltage Compatible • Independent Registers for A and B Buses

74AC11623

Contextual Info: 54AC11623, 74AC11623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0091— 02957, JULY 1987—REVISED MARCH 1990 54AC11623 . . . JT PACKAGE 74AC11623 . DW OR NT PACKAGE Local Bus-Latch Capability Flow-Through Architecture to Optimize PCB Layout TOP VIEW

TJ53L

Abstract: 54AC11646 74AC11646 D2957
Contextual Info: TEXAS I NSTR LOGIC 3i E » m 6^1723 aoaflisi 2 miii3 54AC11646, 74AC11646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS \ — ' V— ) C > TI0097— D2957i JULY 1987— REVISED MARCH 1990 54AC11646 JT PACKAGE 74AC11646 . . . DW OR NW PACKAGE

Contextual Info: TEXAS INSTR LOGIC 31E D • flSb!723 QQ&&&&3 h ■ TII3 54AC11520, 74AC11520 8-BIT IDENTITY COMPARATORS -t-is -n -o o TI0099— D2957, JULY 1987— REVISED JANUARY 1990 Compares Two 8-Bit Words 5 4 A C 1 1 5 2 0 . J P A C K A G E 74AC11520 . DW O R N P A C K A G E

74ACT11643

Abstract: 54ACT11643 D2957 B82524
Contextual Info: 54ACT11643, 74ACT11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0096— D2957, JULY 1987— REVISED MARCH 1990 54ACT11643 . . . JT PACKAGE 74ACT11643 . . . DW OR NT PACKAGE • Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB

Contextual Info: 54ACT11643, 74ACT11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0096— D2957, JULY 1987— REVISED MARCH 1990 Inputs are TTL-Voltage Compatible 5 4 A C T 11 6 43 . . . J T P A C K A G E 7 4 A C T 1 1643 . . . D W O R N T P ACKA G E Flow-Through Architecture to Optimize PCB

54AC11643

Abstract: 74AC11643 D2957
Contextual Info: TEXAS INSTR LOGIC 31E D 0 ^ 172 3 QQÖÖ'ISO b 54AC11643, 74AC11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS ~ T '5 : z ~ 3 i - 0 TI0095— 02957, JU L Y 1987— REVISED M AR CH 1990 Flow-Through Architecture to Optimize PCB Layout S4AC11643 . . . JT PACKAGE

54ACT11623

Contextual Info: 54ACT11623, 74ACT11623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0092— D 2957. JULY 1967— REVISED MARCH 1990 Inputs are TTL-Voltage Compatible 54ACT11623 . . . JT PACKAGE 74ACT11623 . . . OW OR NT PACKAGE TOP VIEW Local Bus-Latch Capability Flow-Through Architecture to Optimize PCB

Contextual Info: TEXAS INSTR LOGIC 31E D Bl 6Tbl753 QQfifl^ST 2 Bi TII3 54AC11646, 74AC11646 OCTAL BUS TRANSCEIVERS AND REGISTERS o , WITH 3-STATE OUTPUTS \ • • • • — J / J " O ' C > TI0097— D2957, JU LY 1987— REVISED MARCH 1990 54AC 11646 . . . J T PACKAGE

Contextual Info: TEXAS INSTR LOGIC B1E 0 5^1723 QDfifi'lSD b 54AC11643, 74AC11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS ~ T '5 : z ~ 3 ( - 0 0 TI0095— 02957, JULY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout S4 A C 1 1643 . JT P A C K A G E

74ACT11643

Contextual Info: 54ACT11643, 74ACT11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0096— D2957, JULY 1987— REVISED MARCH 1990 54ACT11643 . . . JT PACKAGE 74ACT11643 . . . DW OR NT PACKAGE Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout

TI0099-D2957

Abstract: 74AC11520 D2957 65630 P5616
Contextual Info: 54AC11520, 74AC11520 8-BIT IDENTITY COMPARATORS TI0099— D2957, JU LY 1987— REVISED JA N U AR Y 1990 • Compares Two 8-Bit Words 5 4A C 11 5 20 . . . J P A C K A G E 7 4 A C 11520 . . . D W O R N P A C K A G E Flow-Through Architecture to Optimize PCB

TI0094-D2957

Abstract: 54ACT11640 74ACT11640 D2957
Contextual Info: 54ACT11640, 74ACT11640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0094— D2957, JULY 1987— REVISED MARCH 1990 5 4 A C T 1 1640 . . . J T P A C K A G E 7 4A C T 11 6 40 . . . D W O R N T P A C K A G E Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB

Contextual Info: TEXAS INSTR LOGIC 3 1 E T> fllt.1723 0068*141 S BITII 3 54AC11640, 74AC11640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T - S Z r-^ > i ' O O TI0093— 02 9 5 7 , JU LY 1957— REVISED M AR C H 1990 Bidirectional Bus Transceivers in HighDensity 24-Pin Packages

jt50

Abstract: 54AC11640 74AC11640 D2957
Contextual Info: 54AC11640, 74AC11640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0093— D2957, JULY 1987— REVISED M ARCH 1990 54AC11640 . . . JT PACKAGE 74AC11640 . . . DW OR NT PACKAGE Bidirectional Bus Transceivers in HighD ensity 24-Pin Packages TOP VIEW Flow -Through A rchitecture to O ptim ize PCB